Allegro Microsystems, LLC

James McIntosh

Thomas Ross

Robert Douglas Christie

Gianluca Allegrini

Aldo Togneri

Christy Looby

Colin Hall

Robert J Stoddard

Michael James Munroe

Edward Chappell

Peter Morris

Alistair Wood

Douglas Bryce

Walter Morrison Stewart Wilson

An interface circuit, comprising: I/O circuitry configured to couple one or more first terminals with one or more second terminals; a voltage regulator configured to power the I/O circuitry; a restrictor element that is disposed between the voltage regulator and the I/O circuitry, the restrictor element being disposed on a circuit path that connects the voltage regulator to the I/O circuitry, the restrictor element being configured to open the circuit path and disconnect the voltage regulator from the I/O circuitry when an electrical current that is being supplied to the I/O circuitry exceeds a threshold; and a voltage suppressor that is disposed on the circuit path that connects the voltage regulator to the I/O circuitry, the voltage suppressor being disposed between the restrictor element and the I/O circuitry, the voltage suppressor being configured to limit, to a first voltage value, a voltage that is input into the I/O circuitry.

Interface for high-voltage applications

An integrated circuit (IC) includes a level shifter coupled to receive a first supply voltage and a second supply voltage and configured to generate a first output signal and a second output signal in response to an input command signal and an edge detector configured to detect an edge on the second supply voltage and to sink a current from the level shifter in response to detection of the edge in order to prevent a change in logic state of the first output signal or the second output signal. The edge detector can include a positive edge detector configured to generate a positive edge signal in response to detection of a positive going edge of greater than a first predetermined slew rate and a negative edge detector configured to generate a negative edge signal in response to detection of a negative going edge of greater than a second predetermined slew rate.

Level shifter with immunity to state changes in response to high slew rate signals

In one aspect, a circuit includes a gate driver having a first input connected to a first node and a second input connected to a second node; an epi diode connected to the first node; a switch connected to the first node; a capacitor having a top plate connected to the switch and a bottom plate connected to the second node; and a first clamp connected the first node and to the second node. The switch being open isolates the first node from negative transient effects from the top plate of the capacitor.

Gate driver isolating circuit

In one aspect, a gate driver circuit includes a gate driver having a first input connected to a first node and a second input connected to a second node. The gate driver circuit also includes a current source circuit that includes a first transistor and a capacitor having a top plate connected to the source of the first transistor and a bottom plate connected to ground. The gate driver circuit further includes a switch that includes a second transistor. A gate of the second transistor is connected to a drain of the first transistor and a source of the second transistor is connected to the first node.

Switch turn on in a gate driver circuit

In one aspect, an integrated circuit (IC) includes a level shifter configured to generate a first output signal and a second output signal, and to receive an input voltage, a first supply voltage and a second supply voltage; and a state reinforcement circuit configured to maintain a logical state of the second output signal in response to the first supply voltage having a voltage below ground and the input voltage is logical high. If the input voltage is logical high, then the first output signal is logical low and the second output signal is logical high; and, if the input voltage is logical low, the first output signal is logical high and the second output signal is logical low.

Level shifter with state reinforcement circuit

A charge pump includes a first power source having a voltage Vgenerated from a regulated and circuit-limiter supply, a second power source having a voltage Vand a top-off capacitor adapted to be charged to a voltage of the high of Vor Vto a limit of a voltage clamp across the top-off capacitor.

Top-off charge pump and methods of operating same

Methods and apparatus for a voltage regulator having a boost module and a charge pump module. In embodiments, the charge pump module is configured to operate in multiple modes. In embodiments, an IC package includes the boost module and the charge pump with a shared component, such as a capacitor.

Voltage regulator having boost and charge pump functionality

A multi-mode charge pump generates a regulated voltage at an output node from a battery input voltage. The multi-mode charge pump has a plurality of flying capacitors and a plurality of switches coupled to the flying capacitors in order to selectively couple the flying capacitors to the battery, the output node or a reference potential. The regulated voltage is provided across a storage capacitor coupled to the flying capacitors, and the regulated voltage is input to a comparator. The comparator also receives a reference voltage and compares the regulated voltage to the reference voltage to generates an asynchronous regulation signal. A controller in the multi-mode charge pump can automatically transition between operation modes such as a buck mode, a doubler mode and a tripler mode by controlling actuation of the switches in response to the asynchronous regulation signal and clock signals.

Multi-mode charge pump

An isolation switch driver includes a control circuit to control conduction of an isolation switch and a voltage monitor circuit to monitor a control voltage coupled to the isolation switch and to generate a fault indication if the control voltage is less than a predetermined threshold. The isolator driver can drive an isolation switch coupled between a bridge network and a motor in a motor control system. The monitor circuit can monitor a voltage between a gate terminal and a source terminal of the isolation switch and include a resistive element coupled between the gate terminal and the source terminal to generate a current proportional to the VGS voltage, a current mirror to shift a level of the current to a reference potential, and a comparator to compare the level-shifted current to a threshold current.

Circuits and techniques for voltage monitoring of a solid-state isolator

Described embodiments provide a transmitter for transmitting data over a serial bus coupled to the transmitter. The transmitter includes a controller to generate data for transmission by the transmitter. A transmit driver is coupled to the controller. The transmit driver, in response to the generated data for transmission, generates logic transitions on the serial bus. The transmit driver generates low-to-high logic transitions on the serial bus by charging the serial bus by a bus current based on (i) a predetermined initial bias level for a first time period, and (ii) a first predetermined maximum bias level for a second time period. The transmit driver generates high-to-low logic transitions on the serial bus by discharging the serial bus by a bus current based on (i) a pre-charged level of the transmit driver, and (ii) a second predetermined maximum bias level for a third time period.

Non-linear transmit biasing for a serial bus transmitter

A driver circuit is provided for driving a load, such as a multi-phase motor. The driver circuit includes a gate driver for providing a control signal to switching elements coupled to the driver circuit. A first switching element is coupled between a high supply voltage and a switching node of the load, and a second switching element is coupled between the switching node and a low supply voltage. To detect zero crossings of a current through the load, a zero crossing detector includes a first counter coupled to the switching node and a second counter coupled to the control signal. The first counter and second counter count in a predetermined direction based on a detected voltage of the switching node and based on a detected voltage of the control signal, respectively. The zero crossing detector generates an output signal based upon the difference between the first and the second counter.

Motor control current zero crossing detector

Systems and techniques detecting a reverse current are disclosed. An apparatus comprises a switching circuit coupled to a load and a reference node. The switching circuit may be capable of conducting a reverse current from the reference node to the load when a voltage at the load is lower than a voltage at the reference node. A voltage source has a first terminal coupled to the load, a second terminal configured to follow a voltage at the load, and produces a voltage proportional to a voltage drop across the switching circuit. A comparator circuit is coupled to compare a voltage at the second terminal of the voltage source to the voltage at the reference node and configured to indicate when the reverse current has a magnitude greater than a predetermined threshold.

Systems and methods for sensing current through a low-side field effect transistor

An isolation circuit is coupled between motor driver half bridge circuits and an electric motor. A motor controller circuit supplies motor drive signals to the motor driver half bridge circuits. The isolation circuit includes transistors coupled in series with the motor windings. Low to medium power diodes are coupled between a reference voltage source and control terminals of the transistors.

Electric motor drive isolation circuit

A transistor drive circuit uses multi-stage slew rate control to drive one or more switching transistors. After a decision is made to change transistor state, a first drive current may be applied to an input terminal of the transistor for a predetermined time duration. After the predetermined time duration, a second drive current may be applied to the input terminal. When the transition between states is substantially complete, the current drive to the input terminal may be changed to a voltage drive. In some embodiments, the predetermined time duration may be based on the start time of a Miller plateau during the transition period.

Multi-stage slew rate control profiling for transistor drive applications

An electronic circuit for driving an electronic switch includes a first voltage terminal coupled to receive a first voltage from a power supply and a second voltage terminal coupled to receive a second voltage from the power supply. A driver circuit is configured to drive the voltage at a control terminal of the electronic switch to an intermediate voltage level in order to turn on the electronic switch during a high or normal voltage condition. A clamp circuit is configured to clamp the voltage at the control terminal of the electronic switch to the second voltage terminal in order to turn on the electronic switch during a low voltage condition, so that the electronic switch can enhance power provided to a load during the low voltage condition. A low voltage detection circuit detects the low voltage condition and provides a signal to activate the clamp circuit.

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Longniddry, United Kingdom

James McIntosh