Allegro Microsystems, LLC

James McClay

Sundar Chetlur

Maxim Klebanov

Harianto Wong

Vyankatesh Gupta

Gerardo A Monreal

Octavio H Alpago

Nicolas Rigoni

Nicolás Rafael Biberidis

Thomas S Chung

Muhammed Sarwar

Muhammad Sarwar

In one aspect, a flash memory cell includes a well having a first-type dopant, a source having a second-type dopant and formed within the well, a drain having the second-type dopant and formed within the well, a floating gate above the well, a control gate above the floating gate, an oxide compound disposed between the floating gate and the control gate, and a tunnel oxide disposed between the floating gate and the well. The flash memory cell is configured, in one of a program mode or an erase mode, to move an electron from the source to the floating gate. The flash memory cell is configured, in the other one of the program or the erase mode, to move an electron is from the floating gate to the drain.

Flash memory cell structure having separate program and erase electron paths

A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.

Method and apparatus for eliminating bit disturbance errors in non-volatile memory devices

A method for use in a memory device including a first memory matrix is provided, the method comprising: receiving a write request that is associated with a first memory cell, the first memory cell being part of the first memory matrix; copying a content of a second memory cell into a register, the second memory cell being part of the first memory matrix; overwriting the second memory cell with the content of the register when the content of the second memory cell is different from the content of the register; and writing, to the first memory cell, at least a portion of data that is associated with the write request.

Method and apparatus for eliminating EEPROM bit-disturb

Methods for fabricating an integrated circuit having a plurality of gate dielectrics. The methods are provided to include: forming one or more isolation trenches and a first active region and a second active region in a substrate; depositing hard mask material on the substrate; removing a first portion of the hard mask material over the first active region; forming a first oxide layer having a first thickness over the first active region; removing a second portion of the hard mask material over the second active region; and forming a second oxide layer having a second thickness over the first and second active regions such that a thickness of oxide formed over the first active region comprises a sum of the thickness of the first oxide layer and the second oxide layer, and a thickness of oxide formed over the second active region comprises the second thickness.

Method of multiple gate oxide forming with hard mask

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Dudley, MA, United States of America

James McClay