Emc Corporation

Emc IP Holding Company LLC

James Marriott Guyer

William F Baxter

John K Walton

Kendell Alan Chilton

Daniel Castel

Michael Sgrosso

Michael Bermingham

Nhut Tran

Adnan Sahin

Michael J Scharland

Steven T McClure

Jason J Duquette

Robert DeCrescenzo

Ralph C Frangioso, Jr

Patrick J Weiler

Stephen William Daniel

Brandon Barney

A method, computer program product, and computer system for receiving, by a computing device, an I/O request. It may be identified whether the I/O request is eligible for handling via a first path without also requiring handling via a second path. If the I/O request is eligible, the I/O request may be processed via the first path on a host I/O stack without processing the I/O request via the second path on a storage array I/O stack. If the I/O request is ineligible, the I/O request may be processed via the first path on the host.

System and method for accelerated I/O access using storage array driver in Off-the-shelf server

A method, computer program product, and computer system for receiving, by a computing device, an I/O request. It may be identified whether the I/O request is eligible for handling via a first path without also requiring handling via a second path. If the I/O request is eligible, the I/O request may be processed via the first path on a host I/O stack without processing the I/O request via the second path on a storage array I/O stack. If the I/O request is ineligible, the I/O request may be processed via the first path on the host I/O stack and via the second path on the storage array I/O stack.

System and method for accelerated I/O access using storage array driver in off-the-shelf server

A method, computer program product, and computing system for identifying a low-write-frequency portion of a solid-state storage device. If it is determined that the low-write-frequency portion is of sufficient size to function as over-provisioning space for the solid-state storage device, the low-write-frequency portion is utilized as over-provisioning space.

Wear-leveling system and method

A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller passes a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Data storage system having acceleration path for congested packet switching network

A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Data storage system having operation code in address portion for atomic operations

A packet switching network having a plurality of nodes and a network having: a plurality of switches couples to the nodes and links interconnecting ports of the plurality of switches. Each one of the switches has a normal routing table for routing packets from a source one of the nodes to a destination one of the nodes through the network in according to the normal routing table and, for, upon such upon such source one of the nodes detecting a fault in transmission of such packet, routing such to a predetermined designated fault one of the ports of such switch.

Fault isolation and handling in a packet switching network

Data storage system having CPUs adapted to perform a second atomic operation request prior to completion of a first atomic operation request

A queuing system wherein at least one input/output (I/O) interface having an outbound queue. A plurality of processing units is coupled to the at least one I/O interface. Each one of the processing units is coupled to a corresponding processing unit memory. Each one of the processing unit memories has an inbound queue for such coupled processing unit. The at least one I/O interface outbound queue stores outbound information being returned to the I/O interface after being processed by one of the processing units. The I/O interface creates queue indices for storage in the inbound queues of the processor unit memories. The I/O interface includes a translation table, such table storing at a location a producer index for the plurality of processing units and a consumer index for such plurality of processing units.

Data system having a virtual queue

A system interface having a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors are interconnected through a network. A common resource section is provided having a resource shared among the plurality of directors. The common shared resource section includes a shared computer code used by the plurality of directors. The code includes computer code for booting up each one of the plurality directors. The common shared code storage section is interconnected to the directors through the network. A second, redundant common shared resource section is provided. The network is a packet switching network.

Data storage system having shared resource

A system interface having: a plurality of front end directors adapted for coupling to a host computer/server; a plurality of back end directors adapted for coupling to a bank of disk drives; a data transfer section having cache memory; a cache memory manager; and, a message network. The cache memory is coupled to the plurality of front end and back end directors. The messaging network operates independently of the data transfer section and is coupled to the plurality of front end and back end. The front end and back end directors control data transfer between the host computer/server and the bank of disk drives in response to messages passing between the front end directors and the back end directors through the messaging network to facilitate data transfer between host computer/server and the bank of disk drives. The data passes through the cache memory in the data transfer section as such data passes between the host computer and the bank of disk drives. The system includes a cache memory manager having therein a memory for storing a map maintaining a relationship between data stored in the cache memory and data stored in the disk drives. The cache memory manager provides an interface between the host computer, the bank of disk drives and the cache memory for determining for the directors whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. With such an arrangement, the cache memory in the data transfer section is not burdened with the task of transferring the director messaging but rather a messaging network is provided, operative independent of the data transfer section, for such messaging thereby increasing the operating bandwidth of the system interface. Further, the cache memory is no longer burdened with the task of evaluating whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. The cache memory manager, plurality of front end directors, plurality of back end directors and cache memory are interconnected through a packet switching network.

Data storage system having cache memory manager with packet switching network

A computer system for managing a computer network comprises a rack cabinet having a cabinet interior. A plurality of infrastructure connector assemblies are fixedly mounted on the rack cabinet in 1-U boundaries, each infrastructure connector assembly including a signal snap interface connector and a power snap interface connector. A plurality of compute elements are adapted to be slidably disposed within the cabinet interior of the rack cabinet in a stacked relationship, each compute element including at least one infrastructure connector assembly which releasably snap-interconnects with an associated infrastructure connector assembly mounted on the rack cabinet. A distributed power bay is disposed within the rack cabinet and provides central power for the computer system. A rack manager is disposed within the rack cabinet and includes the central video and I/O devices for the computer system. A cabinet controller is disposed within the rack cabinet and is responsible for the management of a geography bus and an intelligent chassis management bus for the computer system.

Growing community of inventors

Northborough, MA, United States of America

James Marriott Guyer