International Business Machines Corporation

Microstrain, Inc.

Other

Lord Corporation

Solarex Corporation

Semivation, LLC

James Marc Leas

Claude Louis Bertin

Kenneth E Beilstein, Jr

Jack Allan Mandelman

John Edward Cronin

Wayne John Howell

Steven Willard Arms

David Lawrence Churchill

Michael John Hamel

David V Horak

William R Tonti

Steven H Voldman

Mark Charles Hakey

George Frederick Walker

Charles Hampton Perry

David J Perlman

Jody John Van Horn

Robert William Koss

Steven J Holmes

Toshiharu Furukawa

Wayne Frederick Ellis

Mark William Kellogg

Erik L Hedberg

David Lewis Gardell

Paul A Rabidoux

Jerzy Maria Zalesinski

Anthony M Palagonia

Bernadette Ann Pierson

Dennis A Schmidt

William H-l Ma

James R Lloyd

Ronald J Prilik

Robert B Phillips, Iii

Bruno Roberto Aimi

Steve Leo Dingle

Patricia McGuinnes Marmillion

Andre Conrad Forcier

David Clifford Long

David Carroll Challener

Krishna Seshan

Steven G Barbee

Peter H Mitchell

Edward W Conrad

Arunava Gupta

Paul E Bakeman, Jr

Joseph M Harvilchuck

Horatio Quinones

Teruhiro Nakasogi

Peter M Elenius

Howard L Kelly

Hans-George H Kolan

Arunachala Nagarajan

Keith F Beckham

Edward Daniel Buker

Morris Shatzkes

Sandra F Leas

Zoe J Leas

Wagih M Wazni

David E Eisenmann

A method of fabricating a single-crystal silicon photovoltaic cell includes providing a single-crystal silicon wafer and a structural support member. The single-crystal silicon wafer has a first major surface and a second major surface. Each major surface extends along a major surface plane. The single-crystal silicon wafer has a thickness greater than 100 micrometers and a dimension greater than 50 mm. The method further includes mounting the structural support member to the first major surface or to the second major surface. The method further includes reducing thickness of the single-crystal silicon wafer to a thickness less than or equal to 100 micrometers while the single-crystal silicon wafer is mounted to the structural support member. The method further includes providing the first major surface with a diffusion and a metalization grid and providing the second major surface with a back surface contact.

Thin single-crystal silicon solar cells mounted to a structural support member and method of fabricating

A device for harvesting an external source of energy includes an electricity generating device and a flexure. The piezoelectric flexure has a first stable bowl-shaped position and a second stable bowl-shaped position. The electricity generating device generates electricity based on movement of the flexure. The flexure remains in the first stable bowl-shaped position until a force provided by the external source of energy causes the flexure to move from the first stable bowl-shaped position toward the second stable bowl-shaped position.

Bowl-shaped wide-band vibration energy harvester

A device for harvesting an external source of energy includes an electricity generating device, a flexure, and a first stop. Displacement of the flexure is limited by the first stop. The flexure has a vibration amplitude, wherein the vibration amplitude is amplitude the flexure would have if unconstrained by the first stop. The first stop allows the flexure to oscillate with a vibration amplitude that is higher than displacement of the flexure as limited by the first stop. The electricity generating device generates electrical energy while the first stop allows the flexure to oscillate with the higher vibration amplitude.

Wide-band vibration energy harvester with stop

A device for harvesting an external source of energy includes an electricity generating device, a flexure, and a restoring spring. The electricity generating device generates electricity based on movement of the flexure. The flexure has a first stable position. When disregarding presence of the restoring spring the flexure also has a second stable position different from the first stable position. The restoring spring is positioned so when the flexure snaps from the first stable position toward the second stable position the restoring spring provides a restoring spring force to restore the flexure toward the first stable position. Substantially greater force is needed to snap the flexure from the first stable position toward the second stable position to overcome the restoring spring force than is required to snap the flexure from the second stable position toward the first stable position.

Wide-band vibration energy harvester with restoring spring

In one embodiment a device comprises a composite structure that includes a piezoelectric flexure and a length-constraining element. The length-constraining element provides the piezoelectric flexure with a bowed shape. The piezoelectric flexure has a first stable bowed position and a second stable bowed position. The length-constraining element is one from the group consisting of a planar sheet and a columnar rod. In another embodiment a device comprises a piezoelectric flexure having a bowl shape. The piezoelectric flexure has a first stable bowl-shaped position and a second stable bowl-shaped position.

Wideband vibration energy harvester

A module includes a first piezoelectric element and first electronic device. The first piezoelectric provides physical support for said first electronic device. One embodiment includes a first insulating layer. The first insulating layer is mounted on the first piezoelectric element. The first electronic device is mounted on the first insulating layer for providing an electronic support function to the first piezoelectric element. In one embodiment the first electronic device includes a rectifier. One embodiment includes multiple contacts to the piezoelectric element each with its own rectifier. Another embodiment includes a stack of piezoelectric elements.

Integrated piezoelectric composite and support circuit

A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.

Carrier for test, burn-in, and first level packaging

A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

Vertical dual gate field effect transistor

A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier. The carrier is formed of a flex material. It can also be formed of printed circuit board material. A window in the flex permits invoking redundancy on each chip after burn-in is complete, significantly improving yield as compared with present schemes that do not permit repair after burn-in.

A synchronized optical clocking signal is provided to a plurality of optical receivers by providing a layer of a high absorption coefficient material, such as SiGe or Ge, on a front surface of a low absorption coefficient substrate, such as silicon. Diodes are formed in the germanium containing layer for receiving an optical signal and converting the optical signal into an electrical signal. An optical clocking signal is shined on the back surface of the silicon substrate. The light has a wavelength long enough so that it penetrates through the silicon substrate to the germanium containing layer. The wavelength is short enough so that the light is absorbed in the germanium containing layer and converted to the electrical clocking signal used for neighboring devices and circuits. The germanium concentration is graded so that minority carriers are quickly swept across junctions of the diodes and collected.

SiGe or germanium flip chip optical receiver

A vertical transistor particularly suitable for high density integration includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

Semiconductor wafer test and burn-in

An optical FET includes one or more light-responsive diodes stacked on the gate. Each diode includes a planar (horizontal) junction. The number of diodes is chosen to achieve a desired gate to source potential difference. An electrical connection connects the diode(s) to the source of the FET.

Optical FET

A memory cell is constructed with one electrode of the transfer device extending over a trench capacitor, saving about 6.5% of cell area. Selective polysilicon for a strap seeded from the trench is grown in the same step in which selective single crystal silicon seeded from the substrate is grown for the transfer device. At least a portion of the node diffusion is located in single crystal epitaxial silicon extending over the trench. The process eliminates the need for a separate strap masking step.

Memory cell with transfer device node in selective polysilicon

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South Burlington, VT, United States of America

James Marc Leas