Micron Technology Incorporated

James M Shaffer

Karl H Mauritz

Glen G Atkins

Michael S Cohen

Salman Akram

Brent Keeth

Eugene H Cloud

Thomas W Voshell

Geary L Leger

Henry D Gerdes

Alex Closson

Defective memory is programmed to have a contiguous address space by dividing the logical address space of the memory into a plurality of address sections. The address section containing the address mapped to a defective memory location is identified. The physical memory locations originally mapped to the addresses in the identified address section are remapped to addresses in an address section at one end of the address space. The addresses in the end address section are disabled. Alternatively, spare memory is provided and the addresses in the end address section are remapped to physical locations in the spare memory. A similar remapping procedure is applied to repair defective data paths in a memory. The remapping procedure is applicable to memory devices or memory modules.

Semiconductor memory remapping

An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary die temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

Repairable wafer scale integration system

A method of forming electrically conductive pillars on a printed circuit board by providing a printed circuit board having a plurality of electrical traces and forming a plurality of elongate, electrically conductive pillars of superimposed layers of solder and conductive polymer on the printed circuit board. The elongate, electrically conductive pillars are connected by a first end to the electrical traces of the printed circuit board and extend substantially perpendicularly from the printed circuit board such that a second end of each of the plurality of elongate, electrically conductive pillars lies in substantially a common plane which is substantially perpendicular to and above said printed circuit board.

Method of forming electrically conductive pillars

An apparatus for wafer scale burn-in and testing of semiconductor integrated circuits and a method for its utilization is disclosed. A wafer is mated to a printed circuit board which electrically contacts the pads on each die using small conductive pillars. Single precise alignment of entire wafer within apparatus allows for testing all the dice on the wafer in parallel, eliminating need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test, thereby increasing throughput.

Wafer scale burn-in apparatus and process

A modular circuit includes a memory module that has an array of memory cells, a communication module that has communication circuitry for coupling signals between the array and external circuitry, and an interconnection module that electrically interconnects the array on the memory module and the communication circuitry on the communication module. The memory and communication modules may also be mounted to the interconnection module. Alternatively, the memory and interface modules may be electrically interconnected and mounted to each other, in which case the interconnection module is not required.

Modular memory circuit and method for forming same

An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary dice temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

An apparatus for wafer scale burn-in and testing of semiconductor integrated circuits and a method for its utilization. A wafer is mated to a printed circuit board which electrically contacts the pads on each die using small conductive pillars. Single precise alignment of entire wafer within apparatus allows for testing all the dice on the wafer in parallel, eliminating need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test, thereby increasing throughput.

A spare memory arrangement in which a defective chip in a memory array can be electronically replaced with a spare chip of identical construction. A defective memory chip is first detected and located by a suitable means, such as an error correction code (ECC), check sum, or parity check. A sparer chip is constructed to be actuated upon a read to the defective memory chip to replace the defective chip with a memory spare chip. The sparer chip includes a cross-point memory (CPM) cell having an address register for receiving data from a central processing unit (CPU) and routing the data to and from the spare memory chip. The cross-point memory (CPM) cell is actuated by control input from the (CPU).

Spare memory arrangement

A circuit that controls, calibrates and monitors critical timing parameters in a computer system or network to prevent loss of, or inaccurate data, when transferring this data.

Timing calibrate and track control circuit

The invention relates to a stacked integrated circuit module 20 which is interchangeable with standard printed circuit boards. Module 20 has two PCBs 22 and 24 and multiple memory ICs 26a-26d mounted on the PCBs. A board alignment support 48 is provided between PCBs 22 and 24 to support the PCBs in a spaced and substantially parallel relation and to provide electrical interfacing between the two PCBs. PCB 22 has an edge connector 44 adapted to be inserted into standard receptacle connectors provided on a mother board. According to this stacked arrangement, memory ICs 26c and 26d are addressable through connector 44, conductive paths formed on PCB 22, board alignment support 48, and conductive paths formed on PCB 24.

Growing community of inventors

Boise, ID, United States of America

James M Shaffer