Sequoia Systems, Inc.

Emc Corporation

James M Nolan

Jack J Stiffler

Michael J Budwey

Jack Justin Stiffler

Stuart P MacEachern

James A Wentworth

Raju C Bopardikar

Jacob Y Bast

Gary A Cardone

Zdenek Radouch

David E Kaufman

Bruce D McLeod

David A Wallace

Richard A Karp

Peter Mark

David Harvey

A data system architecture is described that allows multiple processing and storage resources to be connected to multiple clients so as 1) to distribute the clients' workload efficiently across the available resources; and 2) to enable scaleable expansion, both in terms of the number of clients and in the number of resources. The major features of the architecture are separate, modular, client and resource elements that can be added independently, a high-performance cross-bar data switch interconnecting these various elements, separate serial communication paths for controlling the cross-bar switch settings, separate communication paths for passing control information among the various elements and a resource utilization methodology that enables clients to distribute processing or storage tasks across all available resources, thereby eliminating 'hot spots' resulting from uneven utilization of those resources.

Method and apparatus for implementing high-performance, scaleable data processing and storage systems

Computer system resources shared by several central processing units are allocated by allowing one processing unit to temporarily gain exclusive access to a particular shared resource. Access to a particular resource is controlled by a memory location which contains information representing the current state of the resource and the identity of any processing element currently utilizing the resource. In the case where several resources are interchangeable, the memory location may also contain information regarding the busy/idle states of other interchangeable resources. The memory location can be interrogated by any of the processing elements via command and address information. If the contents of the memory location indicate that the associated resource is not in use, then the interrogating processing element immediately obtains control of the resource. If the resource is in use, the identity of the processing element currently using the resource and any stored resource state information is returned to the interrogating processing element which can then continue processing without the resource or choose another idle resource.

Shared computer resource allocation system having apparatus for

Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed. A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element. At a context switch, the stored information is sequentially written to two separate main memory units. A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity. To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory. The entry indicates whether the corresponding data block has been modified during data processing or written with computational data from the processing element. The storage operations are carried out by high-speed hardware which stores only the modified data blocks. Additional special-purpose hardware simultaneously invalidates all cache memory entries so that a new task can be loaded and started.

Memory back up system with one cache memory and two physically separated

Memory back-up system

A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas. The transfer of the supervisor function from processor to processor is performed by registering the supervisor's identity in a common area in one of the dedicated interface units which area is accessable to all processors in the associated group and using program interrupts generated in the common interface unit to communicate between group processors. Access to the common system bus by the processing elements is controlled by the associated interface units by means of a combination serial/parallel arbitration scheme which increases arbitration speed without requiring a full complement of request/grant leads.

Modular computer system

Circuitry for a fault-tolerant computer is disclosed which circuitry is constructed in two identical halves. Each half, by itself, is not a functionally-complete circuit, however, the two identical halves can be connected together to provide a functionally-complete circuit. Each of the two circuit halves is considerably less complex than a functionally-complete circuit yet, when connected together, the two halves provide fault detection capabilities equivalent to a computer system in which the outputs of two functionally-complete, redundant circuits are compared to detect faults. In particular, each inventive circuit half contains a complete data processing and control unit but only one half of the memory which is necessary for a functionally-complete unit. The processing units on each circuit half operate simultaneously on identical data and the same address information is provided to the memories on each circuit half. To provide error detection, address information and data sent from each control unit to its associated memory is compared between circuit halves. In addition, information provided to the circuits over an external bus or generated by the control unit is encoded with an error-detecting code.

Self-checking computer circuitry

Growing community of inventors

Holliston, MA, United States of America

James M Nolan