Westinghouse Electric Corporation

Northrop Grumman Systems Corporation

James M Mussler

William E Zitelli

Kenneth E Daggett

James A Neuner

Andras I Szabo

Albert W Crew

Jane P Arnold

Mark E Swartz

An apparatus and method for media access control of a first node in a network on a powerline communication medium. The apparatus includes a priority controller for providing a transmit authorization signal. The authorization signal can be responsive to a unique priority of the first node in relation to other nodes in the network, with the priority controller receiving the node's priority from a node network controller in the first node. The apparatus includes an access controller for receiving the transmit authorization signal and, in response, communicating a transmit request signal to the node network controller. The apparatus also includes an arbitration controller for preventing the node from transmitting to the network until a predetermined number of other nodes have been allowed to precedentially access the network. The arbitration controller responds to the priority controller, and sends a transmit inhibition signal to the access controller, inhibiting node transmission irrespective of the authorization signal. The invention also provides a method for communication by a first node in a network having a plurality of nodes, including the steps of sensing a powerline communication medium for the presence of a carrier signal by the first node; inhibiting transmitting by the first node to the network if the presence of the carrier signal is sensed; and transmitting at least one data packet, if the carrier signal is not sensed on the network and the current priority period corresponds with a first predetermined priority period.

Communication apparatus and method

A method of compactly storing digital data includes the steps of sequentially entering a plurality of digital data entries into a shift register having a plurality of stages and summing successive groups of data entries as they are outputted from the shift register to produce singly compressed data entries that are subsequently entered into a second shift register. Sets of singly compressed data entries which are outputted from the second shift register are again added to obtain doubly compressed data entries which are entered into a third shift register. This process continues until a sufficient number of shift registers have been employed to accommodate all of the expected data entries.

Method of compactly storing digital data

A method of determining the rate of change of frequency of a plurality of randomly occurring events begins by counting the number of random events which occur within a plurality of predetermined sampling intervals to obtain a plurality of count values, each corresponding to one of the sampling intervals. These count values are stored in a memory table and the count values which correspond to the most recent set of N of the sampling intervals is summed to obtain a first accumulated count. A second accumulated count is obtained by summing the count values which correspond to a second set of N of the sampling intervals, preceding the most recent set. The rate of change of event frequency is then calculated by dividing the logarithm of (S.sub.1 /S.sub.2) by the number N. The value of the number N is dynamically adjusted for subsequent calculations based on the incoming frequency of random events.

Method for calculating the rate of frequency of random events

A method for automatically calibrating a touch screen used in conjunction with a graphic display is executed prior to every interactive session. Three points, defining perpendicular axes, are displayed and an operator is instructed to touch the touch screen at each of the points in succession. Coordinates for the three points output by the touch screen are checked for reasonableness and perpendicularity. If these checks are passed, a coordinate translation matrix is generated for converting touch screen coordinates into display coordinates.

Automatic touch screen calibration method

A microprocessor-based control system for controlling the speed of a steam turbine by governing the steam supplied thereto from a steam supply source using one or more hydraulically operated servomotor throttle valves is disclosed. The operation of the speed controller is characterized by a plurality of permanently pre-programmed read-only memories containing sets of instructions and data words arranged in an addressable order. The instructions and data words are synchronously processed by the microprocessor as governed by a system clock. Apparatus is provided to initialize the status of the speed controller under the control of the microprocessor in accordance with the processing of one portion of the sets of programmed instructions and data words thereby. The remaining portion of the program is processed by the microprocessor as governed by a real time clock for coordinating the operation of an operator's panel interfaced to the controller and for monitoring the turbine speed and controlling the position of the one or more valve servomotors in accordance therewith. The subportion of the remaining portion of the program primarily characterizing the panel coordination functions is processed during each even period of the real time clock. Accordingly, the subportion of the remaining portion of the program primarily characterizing the turbine speed control is processed during the odd periods of the real time clock.

Microprocessor-based, programmed turbine speed control system

A microprocessor-based turbine speed controller which incorporates a set of permanently programmable memory devices for characterizing the control of turbine speed in real time is disclosed. A speed monitoring interface circuit included in the speed controller is governed by the microprocessor in accordance with the processing of one program stored in one or more of the permanently programmable memory devices to generate speed measurement data words representative of actual turbine speed. In addition, a power-on initialization circuit initializes the microprocessor at the time of power turn-on to process another program stored in one or more of the permanently programmable memory devices for initializing a plurality of predetermined registers contained in the speed controller corresponding to the characterized speed control operation to be performed by each. Further apparatus and programmed instructions for the control thereof are employed to detect a malfunction in program execution by the microprocessor. Additional apparatus is included to provide a speed control signal output and to condition a plurality of digital input and output signals. All microprocessor processing operations are synchronously time sequenced using the signals generated by a system clock.

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Bethel Park, PA, United States of America

James M Mussler