Trw Limited

James M Murduck

John Robert LaGraff

Hugo W-k Chan

Hugo W Chan

Claire L Pettiette-Hall

Arnold H Silver

Gershon Akerling

Robert D Sandell

Kenneth P Daly

An implant patterned superconductive device and a method for indirect implant-patterning of oxide superconducting materials is provided. The method forms a device having an oxide superconducting layer on a substrate, deposits a passivation layer atop the oxide superconducting layer, and implants chemical impurities in a selected portion of the superconducting layer through the passivation layer. This modifies the conductivity of the selected portion of the oxide superconducting layer and electrically isolates the selected portion from the non-selected portion of the oxide superconducting layer. The passivation layer is made of a material less susceptible to implant damage than the oxide superconducting layer to allow inhibition of the oxide superconducting layer while protecting the crystalline structure of the top surface of the oxide superconducting layer and keeping it planarized. The passivation layer is preferably a dielectric material having a crystal lattice structure which is compatible to that of the oxide superconducting layer. The method is especially efficient for the fabrication of devices with multiple layers of oxide superconductive materials because it does not degrade the epitaxial template's crystalline structure.

Implant-patterned superconductive device and a method for indirect ion implantation of superconductive films

A SNS Josephson junction (,) is provided for use in a superconducting integrated circuit. The SNS junction (,) includes a first high temperature superconducting (HTS) layer (,) deposited and patterned on a substrate (,), such that the first HTS layer (,) is selectively removed to expose a top surface of the substrate (,) as well as to form an angular side surface (,) on the first HTS layer (,) adjacent to the exposed top surface of the substrate (,). Ion implantation is used to form a junction region (,) having non-superconducting properties along the angular side surface (,) of the first HTS layer (,). A second HTS layer (,) is then deposited and patterned over at least a portion of the first HTS layer (,) and the exposed top surface of the substrate (,), thereby forming a SNS Josephson junction.

Using ion implantation to create normal layers in superconducting-normal-superconducting Josephson junctions

Method for indirect Ion implantation of oxide superconductive films

The invention relates to a method for producing an electrical connection to a high temperature superconductor (HTS) circuit, where a polymer material is applied to the HTS surface covering the circuit contact disposed on one surface of the HTS circuit, a via is created in the polymer material exposing the circuit contact, a diffusion barrier is applied into the via covering the circuit contact; and, a solder bump is applied to the diffusion barrier.

Process of fabricating high frequency connections to high temperature

A SQUID 10 was multiple junctions, each junction allowing a critical current to flow therethrough. The SQUID 10 comprises a laminar structure including: (a) a substantially planar substrate 12; (b) a first high temperature superconductive layer 14 of substantially uniform thickness deposited on the substrates; (c) a dielectric layer 16 deposited on the first superconductive layer 14, the dielectric layer 16 comprising a planar level segment 18 having two ramp segments defining SQUID junctions at opposing ends 20 and defining SQUID hole; and (d) a second high temperature superconductive layer 24 of substantially uniform thickness deposited on the dielectric layer 16, the second high temperature superconductive layer 24 covering all three segments of the dielectric layer 16. A magnetic field substantially parallel to the substrate applied to the SQUID hole modulates a critical current flowing through the junctions while minimizing magnetic field penetration into the junctions and minimizing SQUID loop inductance.

Superconductive quantum interference device for digital logic circuits

A Josephson junction and a method for its fabrication in which a laminated junction layer is formed in situ on the side edge of a base electrode contact. The laminated junction layer forms the Josephson junction of the present invention and includes an insulating or barrier layer sandwiched between a superconducting base electrode and a superconducting counter electrode. The Josephson junction is formed on the side edge of the base electrode contact to allow very small junction areas to be fabricated using conventional optical lithographic techniques, such as photolithography. The laminated junction layer is formed in situ, with the three layers of the laminated junction layer being formed successively without removing the device from the controlled atmosphere of the deposition system, to prevent contamination of the junction region.

Growing community of inventors

Redondo Beach, CA, United States of America

James M Murduck