Bae Systems Information and Electronic Systems Integration Inc.

Fujitsu Corporation

Fujitsu Network Communications, Inc.

James M Meredith

Curtis M Grens

Richard L Harwood

Thomas A Manning

Stephen A Caldara

Stephen A Hauser

Joseph D Cali

Gregory M Flewelling

Raymond L Strouble

Michael E Gaddis

Gary M Madison

Richard G Bubenik

Randall M White

Justin A Cartwright

Zachary D Schottmiller

A clock alignment system includes a first clock generator generating a first clock signal in a first clock domain and a second clock generator generating a second clock signal in a second clock domain slower than the first clock domain. A coarse delay-locked loop (DLL) generates third clock signals having corresponding phase offsets from the first clock signal, and a fine DLL generates a fourth clock signal by adjusting the phase of a selected one of the third clock signals. The second clock generator generates the second clock signal from the fourth clock signal. A phase detector compares phases of the first and second clock signals. A control circuit aligns the first and second clock signals by using the compared phases to select the third clock signal output by the coarse DLL, and control the phase adjustment by the fine DLL of this third clock signal.

Clock alignment system having a dual-loop delay-locked loop

Techniques are provided for phase-locked loop (PLL) configuration, based on a calibrated lookup table (LUT). A methodology implementing the techniques according to an embodiment includes selecting one of a number of voltage controlled oscillators (VCOs) of the PLL, and selecting a tuning parameter to control the VCO. The method further includes testing the PLL, using multiple loop divider values, to determine a minimum and maximum value that define the lower and upper bounds of a range of loop divider values for which the PLL achieves a locked state while using the selected VCO and tuning parameter. The method further includes storing PLL configuration parameters to an entry in the configuration LUT, the PLL configuration parameters to include an identification of the selected VCO, the selected tuning parameter, the minimum loop divider value, and the maximum loop divider value. The method iterates using additional combinations of selected VCOs and tuning parameters.

Calibrated lookup table for phase-locked loop reconfiguration

Methods and apparatus for scheduling cell transmission over a network link by a switch. The switch includes a plurality of queues associated with each link. Lists of queues are maintained for each link. In one embodiment, each link is associated with more than one type of list (with the list type corresponding to a scheduling category) and more than one prioritized list of each type (with the priority of the list corresponding to a quality of service). The scheduling lists are accessed to permit cell transmission from a queue contained therein in a predetermined sequence as a function of scheduling category, priority within a particular scheduling category and whether the bandwidth requirement for the particular scheduling category has been met. With this arrangement, maximum permissible delay requirements for each scheduling category are met.

Network link access scheduling using a plurality of prioritized lists

Growing community of inventors

Westford, MA, United States of America

James M Meredith