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Lewis Innovative Technologies

Mercury Systems, Inc.

James M Lewis

Dane R Walther

Paul H Horn

Joey R Haddock

Elizabeth B Lewis

A challenge/response system separates a physically unclonable function from the challenge/response. Bits in a challenge are used to qualify random data values. The random data values are permuted to generate a result. The result is used to encrypt a response that is sent in reply to the challenge. Additional permuting mechanisms may be used to further obfuscate the response.

Challenge/response system

An electronic asymmetric unclonable function applied to an electronic system being evaluated includes an electronic system and an AUF array electronically associated with the electronic system. The AUF array includes a plurality of non-identical cells. Each of the non-identical cells includes a test element representing a characteristic of the electronic system being evaluated and a measurement device evaluating the test element. A comparison unit processes an output of the measurement device to provide a multi-bit output value representing a magnitude of differences.

Electronic physical unclonable functions

A self-modifying FPGA system includes an FPGA and a configuration memory coupled to the FPGA for providing the FPGA with configuration data including SAFE configuration data and dormant configuration data. The SAFE configuration data is initially loaded to the FPGA and the FPGA is configured to a safe operating mode. Upon a determination to proceed to a next step of self modification, dormant configuration data contained in the configuration memory is loaded into the FPGA and the FPGA is configured to a secure operating mode.

Self-modifying FPGA for anti-tamper applications

A system employs physical unclonable functions of an integrated circuit for detecting integrated circuits and protecting products and technology from integrated circuits which have been subject to tampering, stressing and replacement, and counterfeit components. The system includes a sensor detecting a characteristic impedance generated as a result of controlled access to a memory device of the integrated circuit. The characteristic impedance is applied in the creation of a discrimination matrix of values based on electrical interface signals for the integrated circuit. The sensor includes a ring oscillator and associated monitoring components. The ring oscillator is composed of the memory device of the integrated circuit and a sensory circuitry, wherein changes in a frequency generated by the ring oscillator is indicative of changes in circuitry.

Method and system for protecting products and technology from integrated circuits which have been subject to tampering, stressing and replacement as well as detecting integrated circuits that have been subject to tampering

A method for combating counterfeiting and tampering of integrated circuits includes the steps providing a programmable logic device, the programmable logic device including an arithmetic circuit implemented into the substrate, and constructing an arithmetic feedback oscillator using the arithmetic circuit. The step of constructing the arithmetic feedback oscillator includes incorporating a feedback loop into the arithmetic circuit and feeding output bits back into an input of the arithmetic circuit. The method also includes the step of selecting input values producing repeating values in a lesser order bit of a product of the arithmetic circuit when first and second input are applied to the arithmetic circuit and monitoring the lesser order bit and determining a predicted pattern.

Method and system for identifying counterfeit programmable logic devices

A sensor system for protecting products and technology from reverse engineering by detecting attempts to probe electronic circuitry includes a sensor electrically linked to electronic circuitry. The sensor detects interaction of probe devices with the electronic circuitry for the purpose of reverse engineering the electronic circuitry. The sensor includes an exciter and an impedance counter linked to the exciter. A count rate of the impedance counter is a function of the impedance of the electronic circuitry due to the fact that oscillation frequency generated by the exciter is also a function of the impedance of the electronic circuitry. The sensor also includes an impedance register storing the binary count value from the impedance counter, wherein after the impedance counter data is transferred into the impedance register, the data is referred to as impedance data. The sensor also includes a reference oscillator monitoring count rate of the impedance counter and a sensor evaluation system comparing the impedance value to threshold values to determine if a significant change has occurred. When changes have occurred this is indicative of abnormal behavior and may be indicative of tampering relating to the evaluation of the electronic circuit for the purpose of reverse engineering.

Method and system for detection of tampering related to reverse engineering

A self-modifying FPGA system includes an FPGA and a configuration memory device coupled to the FPGA for providing the FPGA with configuration information. The configuration memory device is programmed with configuration data and dormant data. The FPGA system is also provided with a configuration assist circuit coupled to the FPGA and the configuration memory device for controlling loading of configuration information from the configuration memory device to the FPGA. A tamper detection system provides a tamper signal to the FPGA, wherein when a tamper signal is received by the FPGA the configuration data is replaced with the dormant data.

An encryption system includes a plurality of encryption operations including individual encryption operations and group encryption operations available for application in the encryption of data. The plurality of encryption operations are selected from the group consisting of functional variance, functional alignment, mathematical offset, wide XOR function, short logical rotation, long logical rotation, functional order, and address encryption. The system includes at least one round of encryption composed of a first encryption operation and a second encryption operation. The first encryption operation is selected from the plurality of encryption operations acting upon input data to generate a first encrypted data set. The second encryption operation is selected from the plurality of encryption operations acting upon the first encrypted data set to generate a second encrypted data set. The first encryption operation and the second encryption operation are different.

Exclusive encryption system

A method and apparatus provides for high-speed switching of high-voltage and high power MOSFET-based solid state relays. A driver for a MOSFET based, high voltage, high current electronic relay includes a current supply for actuating the switching circuit and a transformer arrangement coupled to the current supply for receiving the supply of current from the current supply. The transformer arrangement is adapted for coupling with the switching circuit for selectively applying a predetermined voltage to the switching circuit which establishes the switching circuit in switch conducting or switch isolation.

Driver system for MOSFET based, high voltage electronic relays for AC power switching and inductive loads

Driver system for MOSFET based, high voltage, electronic relays for AC power switching and inductive loads

A MOSFET based, high voltage, high current AC electronic relay includes a MOSFET switching circuit selectively switching between switch conducting and switch isolation. The relay also includes a transformer coupled to the MOSFET switching circuit, the transformer selectively applies a predetermined voltage to the MOSFET switching circuit which establishes the MOSFET switching circuit in switch conducting. In addition, a switching assembly for use in an AC power control system includes a first MOSFET switching circuit and a second MOSFET switching circuit electrically connected between a first terminal and a second terminal, an electrical conducting member positioned between the first MOSFET switching circuit and the second MOSFET switching circuit. The switching assembly also includes a third MOSFET switching circuit electrically connected between the electrical conducting member and ground. Each of the first, second and third MOSFET switching circuits include first and second power MOSFETs and a depletion mode MOSFET. Finally, a MOSFET switching circuit for use in a power control system is disclosed. The switching circuit includes a first power MOSFET, a second power MOSFET and a depletion mode MOSFET.

MOSFET based, high voltage, electronic relays for AC power switching and inductive loads

A high speed binary counter includes a counting first flip-flop for each binary bit, a single AND gate for each lower order binary bit beyond Band B, and at least two AND gates for each higher order binary bit. The counter also includes an input factor delay second flip-flop. The counter is further provided with a mechanism for redundant least significant terms for lesser order bits.

High speed binary counter

A MOSFET based, high voltage, high current AC electronic relay operating with normally closed contacts is disclosed. The relay includes at least one MOSFET switching circuit selectively switching between switch conducting and switch isolation. The at least one MOSFET switching circuit is normally closed and includes a plurality of inputs controlling the operation thereof. The plurality of inputs are connected to at least one rectifier such that a voltage differential exists between any two inputs of the MOSFET switching circuit providing a voltage source maintaining the MOSFET switching circuit normally closed. The relay also includes a control circuit linked to and controlling operation of the first transformer and second transformer. A switch for use in controlling operation of a MOSFET based, high voltage, high current AC electronic relay is also disclosed. The switch includes a key and a receptacle for selectively receiving the key at various positions. The receptacle includes a plurality of contacts for selective engagement with the key. The contacts includes first and second common contacts connecting to a common terminal, first and second relay block contacts connecting to a relay block, a normally closed contact coupled to a normally closed terminal and a normally open contact coupled to a normally open terminal. In use, the key is selectively positioned within the receptacle for placing the relay in an automatic mode, a normal mode or an energized mode.

A MOSFET based, high voltage, high current AC electronic relay. The relay includes a MOSFET switching circuit selectively switching between switch conducting and switch isolation and a first transformer coupled to the MOSFET switching circuit. The first transformer selectively applies a predetermined first voltage to the MOSFET switching circuit which establishes the MOSFET switching circuit in switch conducting. The relay further includes a second transformer coupled to the MOSFET switching circuit. The second transformer selectively applies a predetermined second voltage to the MOSFET switching circuit which establishes the MOSFET switching circuit in switch isolation. The relay is also provided with a control circuit linked to and controlling operation of the first transformer and second transformer.

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Moulton, AL, United States of America

James M Lewis