International Business Machines Corporation

James M Joyce

John M Dinwiddie, Jr

John M Loffredo

Kenneth R Sanderson

Lonnie E Grice

Ernest D Baker

Gustavo A Suarez

Joseph Michael Herko

The functions of two virtual operating systems (e.g., S/370 VM and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. The S/370 processors are alien to the S/88 Operating System, i.e., not in its configuration tables. Means are provided to isolate partner pairs of S/88 processors from the S/88 Operating System and couple the S/88 processors directly to corresponding pairs of S/370 processors for interaction therewith, transparent to the S/88 Operating System.

Isolating a central processing unit from the operating system

The functions of two virtual operating systems (e. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

Uncoupling a central processing unit from its associated hardware for

The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

Method and apparatus for the direct transfer of information between

Fault tolerant data processing system

Providing additional system characteristics to a data processing system

Instability effects over a wide range of static load current conditions in a conventional pulse width modulated (PWM) voltage regulator-converter/power converter circuit configuration having cascaded LC--LC filter networks are eliminated by replacing an inductor, in the averaging filter section of the voltage regulator-converter with the primary winding of a transinductor and by placing the secondary winding thereof in series with an inductor in the output filter section of the power converter. The aforementioned transinductor, in combination with other elements of the system, is designed and configurated such that the closed-loop stability characteristics approach that of a two pole system while maintaining the superior filtering characteristics of a four pole system.

Pulse width modulated voltage regulator-converter/power converter having

Disclosed herein is an improved pulse width modulated (PWM) voltage regulator-converter system which can function, alone, as a switched voltage regulator system or in combination with a switched power converter, synchronized therewith to form an improved voltage regulator-converter/power converter system. In the pulse width modulated voltage regulator-converter embodiment of the invention, secondary windings of a 'current mode' regulator-converter interstage transformer are coupled to regulator-converter power transistors in a push-push circuit configuration. Signals generated by a system clock means and an error signal, derived from the output of an averaging filter, drive a pulse width modulated control means connected to the primary windings of the regulator-converter interstage transformer to thereby increase the maximum regulated output voltage of the voltage regulator-converter system after conditioning in the averaging filter. In the pulse width modulated voltage regulator-converter/power converter embodiment of the invention, the aforementioned output voltage of the voltage regulator-converter system is coupled directly to a switched power converter connected in a push-pull circuit configuration. In turn, additional signals generated by the system clock means switch the power converter in synchronizm with the voltage regulator-converter system.

Growing community of inventors

Boca Raton, FL, United States of America

James M Joyce