National Semiconductor Corporation

Xicor Corporation

Realchip, Inc.

James M Jaffe

William H Owen

John M Caywood

Ping Wang

Joseph Drori

Max C Kuo

Isao Nojima

Jeffrey Sung

Norman E Abt

Reza Moazzami

A random access memory device that partially discharges or precharges a column. The memory device has a memory array with a plurality of columns. Each column includes a plurality of memory cells and a first bitline. The precharge line connects the first bitline to a voltage source to precharge at least a portion of the memory cells in the column before a read operation. Pass devices are connected to the first bitlines from the columns and divide the memory cells into a first section on one side of the pass devices and a second section on an opposite side of the pass devices. If a memory cell in the first section is accessed, the control logic opens the pass device during the read operation so that memory cells in the first section are discharged and memory cells in the second section are not discharged during the read operation. If a memory cell in the second section is accessed, the control logic closes the pass device during the read operation so that memory cells in both the first and second sections are discharged during the read operation.

Apparatus and method for a high-speed memory

A wireless communication system for communicating between a host system and a stand-alone device through an electromagnetic coupling medium is disclosed. The communication system has the capabilities of bi-directional data communications between the host and the stand-alone device and of powering the stand-alone device with energy pulses coupled through the electromagnetic coupling medium from the host. The electromagnetic medium is capable of supporting the bi-directional flow of energy pulses and energy transitions thereof between the host and stand-alone device. In one embodiment, bi-directional communication is provided by transmitting and detecting predetermined numbers of consecutive energy transitions coupled through the medium. Resting durations immediately precede and follow each predetermined number of consecutive energy transitions. In a preferred embodiment of the present invention, the host communicates a first binary value to the stand-alone device by coupling a first predetermined number of consecutive energy transitions to the device and a second binary value to the device by coupling a second predetermined number of consecutive energy transitions. Additionally, the host system receives data from the stand-alone device by first coupling a third predetermined number of consecutive energy transitions to the stand-alone device. The stand-alone device then responds by coupling a predetermined number of energy transitions to the medium during the resting duration following the host's transmission of the third predetermined number of consecutive energy transitions. The number of energy transitions sent by the stand-alone device during this resting duration is related to the value of the data digit being sent to the host.

Wireless powering and communication system for communicating data

An improved EEPROM structure is disclosed which provides protection against external detection of data stored within the array's memory cells via microprobing by causing the array's word lines to de-activate upon an attempted deprocessing of the array. An EEPROM 'protect' cell is connected in parallel between each word line within the array and ground potential. Each of these protect cells has formed therein one or more substantially vertical cavities filled with a high etching film. These cavities are provided in a region adjacent to an end of the protect cell's floating gate such that during an attempted deprocessing of the array using an etching process in order to expose the array's word, bit, and control lines for microprobing, the etchant will rapidly diffuse through these cavities, exposing and discharging the floating gate before fully exposing the word, bit, and control lines. Once discharged, each protect cell shorts its associated word line to ground potential. Holding the word lines at ground potential in such a manner precludes the activation of the word lines and, therefore, effectively prevents the external reading of data stored within the array via microprobing.

Secure non-volatile memory array

An improved EEPROM cell structure is disclosed which provides protection against external detection of data stored within the cell. One or more cavities filled with a high etching film and extending in a substantially vertical direction are provided in a region adjacent to an end of the floating gate such that during an attempted deprocessing of the cell using an etching process, the etchant will rapidly diffuse through these cavities and expose the floating gate via these cavities before exposing and removing the control gate via the insulating layers overlapping the control gate. Any charge once present on the floating gate will dissipate before the control gate can be removed, thereby making it impossible to read data stored within the cell. In another embodiment, a sliver region of the floating gate extends laterally beyond the end of the control gate such that any etchant reaching the control gate will expose the sliver region prior to etching through the control gate, thereby discharging the floating gate before the control gate is removed.

Secure non-volatile memory cell

The endurance of ferroelectric capacitors can be extended by refreshing the ferroelectric material. The ferroelectric material is refreshed by impressing a voltage across the ferroelectric capacitor, which voltage is higher than that which the capacitor experiences during normal operation. A memory array having ferroelectric capacitive cells can be refreshed by first reading the memory cells, temporarily storing the data in associated sense amplifiers, refreshing the memory cells by impressing a higher-than-normal voltage across the ferroelectric cell capacitors, then rewriting the temporarily stored data back into the memory cells. Refresh circuits connected between the drive line and bit line common to a number of cells are driven with voltages which are higher than the memory cell experiences during normal read operations. A V.sub.cc to ground pulse train is applied to the drive line, while an inverted waveform thereof is applied to the bit line during refresh operations.

Refreshing ferroelectric capacitors

A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over standard signal paths of the integrated circuit semiconductor memory array and with standard voltage levels. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundancy apparatus may comprise nonvolatile memory means, such as EEPROM's, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.

Field-programmable redundancy apparatus for memory arrays

A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over the standard signal paths with standard voltage levels of the integrated circuit semiconductor memory array. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundance apparatus may comprise nonvolatile memory means, such as EEPROM's, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.

A ferroelectric random access memory device contains columns of ferroelectric memory cells, each column of memory cells being coupled to a distinct bit line. Each memory cell is selectively coupled to a corresponding bit line by an access control transistor so that only one memory cell in the column is coupled to the bit line at a time. To read the data stored in a selected memory cell reads, the cell is strobed twice, separately sampling the output voltage generated each time. Since the first read is a destructive read, the second read operation always reads the cell in its '0' state. Then the two sampled outputs are compared, and if the first reading exceeds the second by at least a threshold amount then a '1' output value is generated. Otherwise a '0' is the output value. In a preferred embodiment, the time delay between strobing the memory cell and sampling its output is made longer the first time that the cell is read than for the second time that the cell is read. In this way, if the cell is storing a '0' bit, the first read will produce an output voltage that is smaller than it would have been had the first read not been delayed, which helps to ensure that cells storing '0' bit values are properly sensed.

Sense amplifier and method for ferroelectric memory

A ferroelectric memory device includes a preamplifier that couples a bit line to a sense amplifier. The preamplifier both provides additional bit line capacitance needed to enable full switching of the ferroelectric capacitor in a selected memory cell, and data signal amplification needed to obtain a reliable data signals from the memory cells after the memory device has aged and the ferroelectric capacitors in the memory cells are generating relatively small voltage signals. More specifically, the preamplifier of the present invention is a set of capacitors which can be switched between two configurations. In the first configuration, used while strobing a selected memory cell, the capacitors are all connected in parallel to the bit line, thereby providing the bit line capacitance needed to enable full switching of the ferroelectric capacitor in the selected memory cell. In the second configuration, used after the memory cell has been strobed, the capacitors in the preamplifier are disconnected from the bit line, and connected in series so as to multiply the voltage developed on the capacitors while the memory cell was strobed. The resulting multiplied or amplified voltage signal is then processed by a sense amplifier.

Growing community of inventors

Santa Clara, CA, United States of America

James M Jaffe