Hewlett-packard Company

Institute for the Development of Emerging Architectures, L.l.c.

James M Hull

Michael L Ziegler

William R Bryg

Harshvardhan P Sharangpani

Stephen G Burger

Kent G Fielden

K Monroe Bridges

Martin J Whittaker

Michael R Morrell

Hans Mulden

Alejandro Quiroz

Vishal Malik

A method verifies that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically. In accordance with the present invention, a test suite written and compiled in big endian mode is loaded into memory. The test suite is converted to little endian mode and stored back to memory. Next, the processor status is changed from big endian mode to little endian mode, and the test suite is executed. Finally, the results of the test suite are examined to ensure that the processor properly executed the instructions in little endian mode.

Method for verifying that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically

A processor having a large register file utilizes a template field for ening a set of most useful instruction sequences in a long instruction word format. The instruction set of the processor includes instructions which are one of the plurality of different instruction types. The execution units of the processor are similarly categorized into different types, wherein each instruction type may be executed on one or more of the execution unit types. The instructions are grouped together into 128-bit sized and aligned containers called bundles, with each bundle includes a plurality of instruction slots and a template field that specifies the mapping of the instruction slots to the execution unit types.

Processor utilizing a template field for encoding instruction sequences

A computing system includes a memory bus, a main memory, an I/O adapter and a processor. The main memory, the I/O adapter and the processor are connected to the bus. The I/O adapter includes a translation map. The translation map maps I/O page numbers to memory address page numbers. The translation map includes coherence indices. The processor includes a cache and an instruction execution means. The instruction execution means generates coherence indices to be stored in the translation map. The instruction execution means performs in hardware a hash operation to generate the coherence indices.

Coherence index generation for use by an input/output adapter located

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Cupertino, CA, United States of America

James M Hull