Fairchild Camera and Instrument Corp.

Fairchild Semiconductor Corporation

Other

Loral Fairchild Corporation

Fairchild Camera and Instrument Coporation

James M Early

Rudolph H Dyck

Darwin J Prockop

William S Phy

Gilbert F Amelio

Leena M Ala-Kokko

Michael Pack

Loretta D Spotila

Alain Colige

Kevien J Negus

Susanna Annunen

Mirko Vuoristo

Larisa Sereda

Jarmo K&ouml;rkk&ouml;

Petteri Paassilta

Andrea Westerhausen Larson

Tero Pihlajamaa

Constantinos D Deltas

Compositions and methods useful for determining whether a subject has an alteration in a gene encoding a protein chain of Type I or Type IX collagen are described. Novel intronic sequences of five human genes, COL1A1, COL1A2, COL9A1, COL9A2, and COL9A3 are described. Methods of determining the existence in a subject of a pathological condition associated with an altered gene encoding a Type I or Type IX collagen protein chain are provided, wherein such pathological conditions include diseases and disorders which are known to be associated with an altered gene encoding a Type I or Type IX collagen protein chain. Primers, probes, and methods of detecting a genetic predisposition of a subject for a pathological condition associated with an altered gene encoding a Type I or Type IX collagen protein chain are provided. Diseases and disorders for which the methods and compositions of the invention are useful for diagnostic or prognostic purposes include, but are not limited to osteoporosis, osteoarthritis, chondrodysplasia, multiple epiphyseal dysplasia, osteogenesis imperfecta, shortness of stature, scoliosis, low bone density, and degenerative joint disease.

Compositions and methods for detecting altered COL1A1 gene sequences

A self-aligned element antiblooming structure for application to charge-coupled devices includes a region in the substrate in which the charge-coupled device is fabricated into which both a P and an N conductivity type impurity are introduced. By introducing impurities of different diffusivities, a sink region is created between two very narrow antiblooming barriers. Using appropriate process controls, the potential height of the antiblooming barriers may be adjusted to drain excess charge accmulating in the substrate adjacent the antiblooming barriers. In this manner the antiblooming function is accomplished using only a minimal area of the substrate. The invention is applicable to charge-coupled devices utilizing a variety of different clocking schemes, and to charge-coupled device image sensors using buried channels.

Self-aligned antiblooming structure for charge-coupled devices and

A ceramic semiconductor package suitable for high frequency operation includes internal and external ground planes formed on opposite faces of a ceramic base member. The internal ground plane is connected to a ground ring formed on the packaged semiconductor device, and both ground planes are interconnected about the periphery of the package. In this way, a uniform and continuous ground is provided to minimize variations in signal transmission line impedance.

Ceramic package for high frequency semiconductor devices

A method and means for reducing signal propagation losses in very large scale integrated circuits is provided comprising a ground plane located adjacent to, but insulated from, a conductive signal layer overlying an active region in a semiconductor substrate. While, the ground plane is preferrably disposed between the signal layer and the substrate, it may be disposed above the signal layer. Moreover, two or more signal layers may be employed and sandwiched between a pair of ground planes.

Means for reducing signal propagation losses in very large scale

An improved integrated injection logic structure utilizes a current mirror in conjunction with each switching transistor (M.sub.1, M.sub.2) of the integrated injection logic circuit of this invention by connecting one of a plurality of collectors (O.sub.0, P.sub.0) of the switching transistor to the base of said switching transistor. In this manner, the current flowing through conducting switching transistors is limited by the current mirror. This limited current flow through conducting switching transistors, as well as the use of voltage pull up means (D.sub.1, D.sub.2) connected to the collectors of the switching transistors prevents the saturation of conducting switching transistors. This results in an increase in the voltage on the collectors of conducting switching transistors and a decrease in the voltage swing between a logical one and a logical zero, thereby substantially increasing the speed of the integrated injection logic circuit of this invention as compared to prior art integrated injection logic circuits. The voltage pull up means connected to the collectors of the switching transistors may comprise resistors or preferably forward biased Schottky diodes connected between a voltage source (V.sub.dd) and the collectors of the switching transistors. This invention is also suitable for use in MOS circuits.

Schottky shunt integrated injection

A self-aligned element antiblooming structure for application to charge-coupled devices includes a region in the substrate in which the charge-coupled device is fabricated into which both a P and N conductivity type impurity are introduced. By introducing impurities of different diffusivities, a sink region is created between two very narrow antiblooming barriers. Using appropriate process controls, the potential height of the antiblooming barriers may be adjusted to drain excess charge accumulating in the substrate adjacent the antiblooming barriers. In this manner the antiblooming function is accomplished using only a minimal area of the substrate. The invention is applicable to charge-coupled devices utilizing a variety of different clocking schemes, and to charge-coupled device image sensors using buried channels.

Self-aligned antiblooming structure for charge-coupled devices

The area circumscribed by the current path on an integrated circuit chip is diminished, to thereby reduce the inductance of the chip and the likelihood of inductively generated errors, by disposing the bonding pads, through which the current source and current sink are respectively connected to logic gates, physically adjacent to one another. A further reduction in the area of the current loop is obtained by locating power and ground busses adjacent to one another relative to the logic gates. These two busses can be superposed one over the other on different metallic layers of the chip, so that the space between them is only the thickness of the isolation layer which separates the two metallic layers. The distribution of voltage to the logic gates is made uniform by varying the widths of the busses along their lengths in accordance with the currents they carry, and by ensuring that the total length of the current path for the gates is the same for every gate.

Integrated circuit chip wiring arrangement providing reduced circuit

Semiconductor memory devices are tested by using a special purpose computer which uses simple test patterns to determine the weakest bits of the device and then tests only these relatively few 'weak bits' and structurally and operationally adjacent bits using highly complex test patterns to determine if the device is functioning properly. This procedure considerably reduces testing time over that required using prior art techniques.

Method for semiconductor memory testing

A charge coupled distributed amplifier comprises a first plurality of charge storage wells arranged along a first selected line, a second plurality of charge storage wells arranged along a second selected line, and a multiplicity of amplifier means, each amplifier means electrically coupling one charge storage well in the first plurality of wells to a corresponding charge storage well in the second plurality of wells. Charges are driven along the first and second pluralities of charge storage wells in synchronization. The same charge in the first plurality of charge storage wells creates an additional increment of charge in each charge storage well connected to the output of each amplifier means which adds in that well to the previously accumulated charge in the second plurality of charge storage wells. Thus a given amount of input charge is amplified coherently to produce a detectable output signal.

Charge coupled amplifier

A reference voltage generator for generating reference voltages for use in charge-coupled devices includes a means for generating a charge whose magnitude lies between a first charge representing a number in an n-dimensional logic system and a second charge representing another number in an n-dimensional logic system, comparison means electrically coupled to the means for generating a charge, the comparison means generating a voltage representative of the charge and comparing the voltage with an instantaneous reference voltage to provide an indication of the relative magnitudes of the voltage and the instantaneous reference voltage, and feedback means electrically coupled to the comparison means for producing an instantaneous reference voltage and including a means for providing an incremental adjustment to the instantaneous reference voltage in response to the indication of relative magnitude, the incremental adjustment serving to bring the value of the instantaneous reference voltage closer to the value for the voltage.

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Palo Alto, CA, United States of America

James M Early