Hewlett-packard Development Company, L.P.

Hewlett-packard Company

James M Dewey

David M Hagen

Jon L Ashburn

Theodore G Rossin

Jayen J Desai

Maynard Darvel Hammond

William J Edwards

Zachary T McCourt

David Purvis

A fluid container that includes body that provides a fluid reservoir. Additionally, the fluid container can also include an outlet structure. The outlet structure can include a conduit that extends from an outlet of the fluid container to the fluid reservoir. Moreover, the fluid container can include an outlet barrier and an interior barrier. The outlet barrier can be positioned within the conduit of the outlet structure in proximity to the outlet of the fluid container. Additionally, the outlet barrier can be structured to receive an inlet extension of a container device. The interior barrier can be positioned within the conduit of the outlet structure in proximity to the fluid reservoir. Additionally, the interior barrier can be displaceable relative to the outlet structure by the inlet extension.

Output mechanism for a fluid container

One exemplary device has a plurality of leads with termination impedances, and a standard impedance. Among the termination impedances are master impedances arranged to be calibrated by comparison with the standard impedance and slave impedances arranged to be calibrated in accordance with an associated master impedance.

On-die impedance calibration

The present invention provides a method and apparatus for receiving and synchronizing data transmitted to a host interface unit of a graphics memory system on the rising and falling edges of a strobe signal in accordance with an accelerated graphics port (AGP) specification. An inner loop synchronization component, which is comprised in the host interface unit of the graphics memory system, receives data transmitted to the host interface unit on the falling and rising edges of a strobe signal and synchronizes the data to a PCI clock signal. The inner loop synchronization component comprises a first data transfer unit, a second data transfer unit and a control unit. The first data transfer unit comprises logic configured to capture the data transmitted on the falling edge of the strobe signal and to delay the captured data a predetermined number of cycles of the PCI clock before outputting the captured data from the first data transfer unit. The control unit detects the falling edge of the strobe signal and generates one or more timing signals based on the strobe signal. The rising edge of the strobe signal may or may not occur within the PCI clock cycle in which the falling edge of the strobe signal occurs. The second data transfer unit receives the timing signals generated by the control unit and utilizes the timing signals to capture the data transmitted on the rising edge of the strobe signal. The second data transfer unit then delays the captured data a predetermined number of cycles of the PCI clock before outputting the captured data from the second data transfer unit. The timing signals generated by the control unit are utilized by the second data transfer unit to ensure that the data transmitted on the rising edge of the strobe signal is output from the second data transfer unit in the same cycle of the PCI clock in which the data transmitted on the falling edge of the strobe signal is output from the first transfer unit.

Method and apparatus for synchronizing data received in an accelerated

Apparatus for performing floating point divide operations includes a divider and a comparator. The divider performs a floating point divide operation on a floating point numerator and a floating point denominator. The comparator performs a comparison of the floating point denominator, except for a sign bit of the floating point denominator, with a floating point value of 0.0. A logic element, responsive to a control signal indicative of the floating point divide operation, provides to the comparator equal sign bits associated with the floating point denominator and the floating point value of 0.0. A result of the comparison indicates a divide by zero operation and is independent of the sign of the floating point denominator. The result of the comparison is used to determine a course of action before the divide operation is completed.

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Ft. Collins, CO, United States of America

James M Dewey