Sun Microsystems, Inc.

James M Byrd

Ebrahim Hashemi

John C Schell

Alex Umino

Manuel Cisneros

The present invention permits error detection to be performed on a word basis (e.g., 32 bits in parallel). An exclusive OR function is performed on each bit of data and cyclic redundancy code (CRC) bit in parallel. If a feedback value (e.g., a standard poly divider) is a logical one it is also included in the exclusive OR function. The present invention is readily adaptable for use with a variety of CRC polynomials (e.g., any Galois Finited Field Equation with primitive irreducible polynomials over GF(2) with linearly independent roots and the reciprocal polynomial with linearly independent roots. In one embodiment, each data word is effectively multiplied by alpha to the first power, where alpha is a root solution to the applicable polynomial utilized to calculate the CRC. In one exemplary implementation of the present invention, the instructions are in assembly language configured with a machine instruction shift through carry.

Accelerated Galois data integrity crosscheck system and method

A method of testing error correction/detection logic may involve providing each of a set of n data bit combinations to the error correction/detection logic. Each data bit combination has n bits, and the n data bit combinations may be created by creating an initial data bit combination whose data bits have the same logical value and then shifting a bit having the opposite value across the initial data bit combination. In response to being provided with the n data bit combinations, the error correction/detection logic generates a set of check bits for each of the n data bit combinations. The set of check bits generated by the error correction/detection logic for each of the n data bit combinations may then be verified.

System and method for verifying error detection/correction logic

A data storage subsystem including an array of storage devices and a storage controller is disclosed. In one embodiment, the array of storage devices stores information in multiple stripes. Each stripe may include a plurality of data blocks and redundancy information in the form of plurality of redundancy blocks. The redundancy information may be generated using an nth order generator polynomial such as a Reed Solomon code. The storage controller may be configured to perform modified read/write stripe updates by: (a) reading original data from a subset of data blocks in a target stripe; (b) reading the original redundancy information for that stripe; (c) comparing the original data with the new data to determine a data difference; (d) calculating a redundancy difference from the data difference; (e) applying the redundancy difference to the original redundancy information to obtain updated redundancy information, (f) writing the new data and updated redundancy information to the target stripe. Multiple erasure correction is also contemplated.

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Fremont, CA, United States of America

James M Byrd