Trw Limited

Northrop Grumman Systems Corporation

James M Anderson

Eric L Upton

Gershon Akerling

Henry T Nicholas

Vincent J Demaioribus

Andrew R Coulson

Jason S Kim

Edward M Garber

Richard A Lewis

John W Spargo

Benjamin Tang

A communications apparatus and method use tapped delay lines as multiplexers and demultiplexers. In one embodiment, a receiver () uses a tapped delay line () as a demultiplexer to acquire a burst communication at very high data rates in the range of 2.5 to 80 Gbps with low preamble overhead. A sliding window correlator () continually samples the delay line () to determine when a PN encoded word is contained therein. The transmission frequency is pre-acquired before any data is present through the use of a ring oscillator frequency calibration loop () that is imbedded within the tapped delay line ().

Burst communications apparatus and method using tapped delay lines

A signal equalizer that employs micro-electromechanical machine devices for the tap weight controllers. The equalizer includes a substrate on which is formed a forward transmission line rail and a return transmission line rail. A cantilever stanchion is also formed on the substrate that runs parallel with the transmission line rails. A series of spaced apart cantilevers are pivotally mounted to the cantilever stanchion, and extend over the transmission line rails to define a gap therebetween. A weight tap line is coupled to each cantilever, and is responsive to a DC weight signal that controls the position of the cantilever to set the gap between the cantilever and the transmission line rails. A distorted signal is coupled from the forward transmission line rail to the return transmission line rail through the cantilevers.

EHF equalizer implemented with MEMs tap weight controls

A method for packaging integrated circuits in a wafer format that eliminates wire bonds. A wafer substrate on which the integrated circuits have been fabricated is patterned and etched to form signal and ground via through the substrate. A back-side ground plane is deposited in contact with the ground vias. A protective layer is formed on the top surface of the substrate, and a protective layer is formed on the bottom surface of the substrate, where the bottom protective layer fills in removed substrate material between the integrated circuits. Vias are formed through the bottom protective layer, and the wafer substrate is diced between the integrated circuits.

Method for packaging integrated circuit chips

A configurable circuit array that includes a matrix of cells, where each cell includes interconnected analog and/or digital circuit elements. The cells are fabricated on a common semiconductor substrate, and are electrically isolated from each other. The circuit elements in the cells are electrically coupled to circuit elements in other cells, and are electrically coupled to bonding pads by coaxial transmission lines capable of transmitting extremely high frequency signals. The transmission lines include a center conductor and first and second shield conductors, where the shield conductors prevent cross-talk interference. The transmission lines extend vertically from the substrate until they are a suitable distances above the circuit elements in the cell. From there, the transmission lines extend horizontally relative to the substrate to the opposite end connection point, where they again extend vertically down to the substrate.

Configurable amplifier array incorporating programmable EHF transmission lines

A semiconductor device, a microelectromechanical system package and a method of making the same utilize high performance vias for vertical IC packaging. A semiconductor die of the device/package has a substrate with integrated circuitry formed on a front side of the substrate. A metal bonding pad overlies the substrate on the front side of the substrate and is electrically connected to the integrated circuitry. A solder bump is located on the metal bonding pad. An electrically conductive via extends through the substrate from the metal bonding pad to a back side of the substrate where the via forms a side wall of a via hole. A plurality of the substrates are stacked on one another with the outer end of the solder bump of one substrate fitting within the via hole of an adjacent substrate. During reflow soldering, surface tension forces of the molten solder bump self-align the substrates.

High performance vias for vertical IC packaging

A packaged die ( ) for an integrated circuit ( ) that eliminates the wire bonds required in the prior art, and provides integrated circuit packaging while the circuit ( ) is still in a wafer format. A wafer substrate ( ) on which the integrated circuits ( ) have been fabricated is patterned and etched to form signal and ground vias ( ) through the substrate ( ). A back-side ground plane ( ) is deposited in contact with the ground vias ( ). A protective layer ( ) is formed on the top surface ( ) of the substrate ( ), and a protective layer ( ) is formed on the bottom surface ( ) of the substrate ( ), where the bottom protective layer ( ) fills in removed substrate material between the integrated circuits ( ). Vias ( ) are formed through the bottom protective layer ( ), and the wafer substrate ( ) is diced between the integrated circuits ( ).

High power chip scale package

An extended play radio video cassette recorder (EPRVCR) capable of receiving and recording audio and video signals transmitted over a radio frequency channel is provided. The EPRVCR includes a videocassette recorder (VCR) and a tuner capable of receiving of radio frequency signals and television frequency signals electrically connected to the VCR. Method for broadcasting and receiving a composite video and audio signal over a radio frequency for subsequent recording by an extended play radio video cassette recorder is also provided. The method includes the steps of providing a VCR having a tuner capable of receiving radio frequency signals; broadcasting audio on a preselected baseband radio frequency; broadcasting a visual image on a subcarrier sideband of the preselected baseband frequency; and receiving the audio and visual image using the tuner of the VCR. The VCR is also capable of recording the audio and video image simultaneously onto a single video cassette. The EPRVCR is also capable of playing the audio and visual image through the VCR for display on a monitor. In an embodiment, the tuner is a direct digital frequency synthesis tuner.

Extended play radio vision cassette recorder system and method of operating same

The chip-to-board (or chip-to-MCM) connection assembly and method therefor features a semiconductor chip (,) having a front surface (,) on which external terminal pads are provided; a board or MCM (,) having a surface (e.g., a recessed surface) at a first side thereof to which the rear surface (,) of the chip is affixed; and a connection carrier (,), disposed as an overlay, which electrically links the chip and the board or MCM. In this assembly scheme, the connection carrier (e.g., a bump carrier) which is affixed to both the chip and the board or MCM, contains all required signal line tracings (,) to provide the electrical interconnection between the semiconductor chip and the board or MCM. The bump carrier replaces all bond wires (,) and the like and can include support/control circuitry, passive and/or active, associated with, for example, high-speed/high-power IC chips (,). The connection carrier (,) is provided with the electrical contacts (,) such as bump electrodes each interconnecting a contact location (,) at the surface side of the connection carrier facing the semiconductor chip and the oppositely disposed (i) external pad on the chip or (ii) external pad or landing (,) at a side of the board (,) facing the connection carrier (,). Heat generated during operation is released through the rear side of the semiconductor chip (,), which is affixed to the board or MCM (,).

Chip-to-board connection assembly and method therefor

A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer.

Adaptive configurable gate array

A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer. Means are also disclosed for an improved E-beam lithographic apparatus which permits an IC chip to be placed on an area of a wafer that is occupied by a marker, providing a wiring or macro design that avoids the marker.

A current limiting circuit and technique is provided for preventing excessive current supplied to a circuit and for providing self-recovery characteristics thereto. The current limiting circuit includes an input for receiving a supply voltage for supplying power to the monitored circuit and an output for providing the power to the desired circuit being monitored. The circuit employs a drive transistor having a source connected to the input and a drain connected to the output. The drive transistor further includes a gate for receiving a control signal. A current mirror circuit is provided for sensing a current overload and adjusting the control signal to indicate the amount of current drawn. During normal current draw, the circuit provides the supply voltage as the output. When excessive current draw is detected, the drive transistor is turned off and the output current is thereby cut off. When the current decreases to normal current loads, the drive transistor is turned back on. In addition, a reset signal may be further generated when excessive current is detected to reset the internal logic on a chip, so as to correct the problem causing the excessive current draw. Furthermore, the monitored circuit and herein described current limiting circuit may be fabricated together on the same die or chip.

Growing community of inventors

Huntington Beach, CA, United States of America

James M Anderson