International Business Machines Corporation

James Lyle Peterson

Ahmed Gheith

Patrick Joseph Bohrer

Ramakrishnan Rajamony

Elmootazbellah Nabil Elnozahy

Malcolm Scott Ware

Freeman Leigh Rawson, Iii

Hazim Shafi

Heather Lynn Hanson

David Brian Glasco

Bishop Chapman Brock

Ronald Lynn Rockhold

Christian Lita

Richard Ormond Simpson

Craig Alan Bennett

Stephen Edwin Smith

Clement Richard Attanasio

Joseph Raymond Thompson

Christos Alkiviadis Polyzois

Michael Thomas Collins

Maria Angela Butrico

Weining Gu

A method for managing data access in a mobile device is provided in the illustrative embodiments. Using a data manager executing in the mobile device, a data item is configured in a data model. A value parameter of the data item is populated with data and a status parameter of the data item is populated with a status indication. A subscription to the data item is received from a mobile application executing in the mobile device. In response to the subscription, the data and the status of the data item are sent to the mobile application.

Managing data access in mobile devices

Creating a thread of execution in a computer processor, including copying, as indicated by a hardware processor opcode having been specified by a user-level process, data from a first set of registers to a second set of registers, wherein the first set of registers is associated with a parent hardware thread, wherein the second set of registers is associated with a child hardware thread, wherein the child hardware thread is in a wait state, and changing, as indicated by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state.

Creating a thread of execution in a computer processor

A method for a framework for scheduling tasks in a multi-core processor or multiprocessor system is provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.

Framework for scheduling multicore processors

A first set of one or more hardware threads for receiving messages sent from hardware threads are registered. After receiving indications of a message location value and a number, the message location value is increments and sent to a different hardware thread of the first set of one or more hardware threads until the message location value has been incremented the number of times or a criterion for interrupting the incrementing and sending is satisfied. An actual number of times the message location value was incremented is indicated to a hardware thread that sent the indications of the message location value and the number.

Inter-thread data communications in a computer processor

Analyzing simulated operation of a computer including loading user-defined dynamically linked analysis libraries that each include specifications of events to be traced for analysis, including: executing, in separate hardware threads, one trace buffer handler for each analysis library, and associating, with each trace buffer handler, one or more analysis functions; translating static binary instructions for the simulated computer into binary instructions for the executing computer, including: inserting, into the translation, implementing code for each specification of an event to be traced and inserting, into the translation for each static instruction, a memory address of a separate static instruction buffer; executing the translation, including executing the implementing code and generating, in a trace buffer, one or more trace records for each specified event; and processing the trace buffer, including calling analysis functions and associating by the analysis functions through the separate static instruction buffers event analysis data with static instructions.

Analyzing simulated operation of a computer

Inter-thread data communications in a computer processor with multiple hardware threads of execution, each hardware thread operatively coupled for communications through an inter-thread communications controller, where inter-thread communications is carried out by the inter-thread communications controller and includes: registering, responsive to one or more RECEIVE opcodes, one or more receiving threads executing the RECEIVE opcodes; receiving, from a SEND opcode of a sending thread, specifications of a number of derived messages to be sent to receiving threads and a base value; generating the derived messages, incrementing the base value once for each registered receiving thread so that each derived message includes a single integer as a separate increment of the base value; sending, to each registered receiving thread, a derived message; and returning, to the sending thread, an actual number of derived messages received by receiving threads.

Creating a thread of execution in a computer processor includes an apparatus for copying data from a first set of registers to a second set of registers. The first set of registers is associated with a parent hardware thread and the second set of registers is associated with a child hardware thread. The copying is indicated by a hardware processor opcode called by a user-level process. The copying is performed with no operating system involvement. The child hardware thread is in a wait state. Creating the thread also includes changing, as indicated by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state. The ephemeral run state indicates a lack of operating system support structures for the child hardware thread.

Creating a thread of execution in a computer processor without operating system intervention

A system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.

A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to move the virtual memory pages according to the new page mapping, and then allows access to the virtual memory pages using the new page mapping while the memory controller is still copying the virtual memory pages to the set of physical memory pages. The memory controller can use a mapping table which temporarily stores entries of the old and new page addresses, and releases the entries as copying for each entry is completed. The translation lookaside buffer (TLB) entries in the processor cores are updated for the new page addresses prior to completion of copying of the memory pages by the memory controller. The invention can be extended to non-uniform memory array (NUMA) systems. For systems with cache memory, any cache entry which is affected by the page move can be updated by modifying its address tag according to the new page mapping. This tag modification may be limited to cache entries in a dirty coherency state. The cache can further relocate a cache entry based on a changed congruence class for any modified address tag.

Superpage coalescing which supports read/write access to a new virtual superpage mapping during copying of physical pages

An extended register processor includes a register file having a legacy register set and an extended register set. The extended register set includes a plurality of extended registers accessible only to extended register instructions. The processor maps extended register references to physical extended registers at run time. The processor includes a configurable extended register mapping unit to support this functionality. The mapping unit is accessible to an instruction decoder, which detects extended register references and forwards them to the mapping unit. The mapping unit returns a physical extended register corresponding to the extended register reference in the instruction. The mapping unit is configurable so that, for example, the mapping is specific to a code block. An extended register allocation instruction causes the processor to allocate a portion of the extended register set to the code block in which the declaration is located and to configure the mapping unit to reflect the allocation.

Extended register bank allocation based on status mask bits set by allocation instruction for respective code block

A multiprocessor system includes a plurality of data processing nodes. Each node has a processor coupled to a system memory, a cache memory, and a cache directory. The cache directory contains cache coherency information for a predetermined range of system memory addresses. An interconnection enables the nodes to exchange messages. A node initiating a function shipping request identifies an intermediate destination directory based on a list of the function's operands and sends a message indicating the function and its corresponding operands to the identified destination directory. The destination cache directory determines a target node based, at least in part, on its cache coherency status information to reduce memory access latency by selecting a target node where all or some of the operands are valid in the local cache memory. The destination directory then ships the function to the target node over the interconnection.

Directory based support for function shipping in a multiprocessor system

An Internet client is provided with a SOCKS server. The client comprises a processor having an operating system, and a suite of one or more Internet tools. The SOCKS proxy server includes means for intercepting and servicing connection requests from the Internet tools. Preferably, the proxy server has a predetermined Internet Protocol address, preferably the loopback address. If the loopback address is not available on the protocol stack, a redirecting mechanism is used to redirect connection requests associated with stale IP addresses to a current IP address. The SOCKS server includes a filtering mechanism for filtering connection requests to particular servers, and a monitoring mechanism for monitoring network IP activity.

Client side socks server for an internet client

A method for initializing variables within class objects in a statically loaded object-oriented programming language. A two-phase flooding algorithm is utilized to initialize the core variables within each class along with those variables needed to be initialized before the core variables. An initialization algorithm is performed within each of the class objects in a recursive manner. Once a class object has begun the initialization process internally, calls to again begin the initialization process within that class object from another class object will result in a return in order to prevent duplicates of the initialization process from being performed within each of the class objects.

System and method for initializing variables in an object-oriented program

A method and apparatus for managing memory allocation. Each memory block category contains memory blocks. A request, including an object size, is received to allocate memory to an object. An available memory block is allocated to the object if the memory block category for size corresponding to the object size of the object contains an available memory block. An available memory block from a memory block category having a memory block size larger than the object size is located if an available memory block is absent in the memory block category for sizes corresponding to the object size. The located available memory block is partitioned into memory blocks, having a size corresponding to the object size. A partitioned memory block from the partitioned memory blocks is allocated to the object.

Method and apparatus for efficiently allocating objects in object oriented systems

A data processing system includes a plurality of processing nodes that each contain at least one processor and data storage. The plurality of processing nodes are coupled together by a system interconnect. The data processing system further includes a configuration utility residing in data storage within at least one of the plurality of processing nodes. The configuration utility selectively configures the plurality of processing nodes into either a single non-uniform memory access (NUMA) system or into multiple independent data processing systems through communication via the system interconnect.

Growing community of inventors

Austin, TX, United States of America

James Lyle Peterson