Altera Corporation

Intel Corporation

Xerox Corporation

James Loran Ball

Sean R Atsatt

Ravi Prakash Gutala

Scott J Weber

Aravind Raghavendra Dasu

Kevin Clark

Dheeraj R Subbareddy

Ankireddy Nalamalpu

Kavitha Prasad

Sharath Raghava

Harsha Gupta

Jeffrey Orion Pritchard

Philippe Molson

David James Lau

Jarrod Colin James Blackburn

Jesse Kempa

Jun Pin Tan

Simon S Chong

James R Lawson

Michael David Hutton

Mahesh A Iyer

Eriko Nurvitadhi

Donald James Curry

Dana How

Jeffrey Christopher Chromczak

Timothy Allen

Eng Ling Ho

Stuart L Claassen

Archanna Srinivasan

Todd W Thayer

David Kasle

Danny L Gepford, Jr

An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.

Multi-purpose interface for configuration data and user fabric data

Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

Network-on-chip (NOC) with flexible data width

A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration.

Three dimensional programmable logic circuit systems and methods

An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

Interface for parallel configuration of programmable devices

Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.

Processors operable to allow flexible instruction alignment

An integrated circuit may include user storage circuits and scan storage circuits. The scan storage circuits may store data from the user storage circuits and provide the data to a user interface during a read-back operation. The user storage circuits may store data from the scan storage circuits, which the scan storage circuits may have received from the user interface during a write-back operation. The scan storage circuits may be arranged in a scan chain and controlled by a local control circuit. The integrated circuit may include multiple local control circuits that each control a sector of the integrated circuit. The local control circuits may communicate with a global control circuit over a communication network, and the global control circuit may communicate with the user interface.

Techniques for using scan storage circuits

Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the processes. Having separate read and write processes allows an arbitrary number of sequential reads/writes to occur in any order, subject to buffer size, allowing bursting/sequential transactions that are more efficient than random accesses.

High-level language code sequence optimization for implementing programmable chip designs

Methods and apparatus are provided for implementing circuitry operable to perform barrel shifting, multiplication, and rotation operations in hard coded logic on a programmable chip. A hard coded multiplier is augmented using multiplexer circuitry, a logical operation, and a bypassable 2^N functional block. Based on control signals, the multiplexer circuitry can be used to select a rotation, multiplication, or barrel shifted output. Multiplexer control signals also provide sign information associated with operands passed to the multiplier. A single augmented multiplier can perform barrel shifting, rotation, or multiplication operations. Inputs of a multiplier can also be selectively grounded to allow the multiplier to perform logic operations.

Multiplier operable to perform a variety of operations

Systems and methods for using an internal read only memory (ROM) to configure a logic device are described. The ROM and the logic device may be located on a single chip. The ROM may be adapted to store highly compressed configuration images and be non-reprogrammable. The logic device may be configured based on the compressed configuration image.

Logic device having a compressed configuration image stored on an internal read only memory

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Santa Cruz, CA, United States of America

James Loran Ball