Intel Corporation

Vintomie Networks B.v., LLC

Integrated Device Technology, Inc.

Keyeye Communications

James Little

Hiroshi Takatori

Marwan M Hassoun

David Erich Tetzlaff

Scott Chiu

Chang-Chi Liu

Jonathan Lee Kennedy

Jeff Illgner

Michael Shaw

Andrea Betti-Berutto

Shawn Parker

Christopher Saint

Sushil Kumar

Nikos Kaburlasos

Kenneth Colin Dyer

Susumu Hara

Perry Leigh Heedley

Russell Byrd

Vaishali Nikhade

David Vieira

Maoyou Sun

An e-band transceiver includes a transmitter circuit and a receiver circuit. The transmitter circuit includes a surface mounted technology (SMT) module on which is mounted a silicon-germanium (SiGe) bipolar plus CMOS (BiCMOS) converter, a gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) output amplifier coupled to the SiGe BiCMOS converter, and a microstrip/waveguide interface coupled to the GaAs pHEMT output amplifier. The receiver circuit of the e-band transceiver includes a receiver-side SMT module on which is mounted a receiver-side SiGe BiCMOS converter, a GaAs pHEMT low noise amplifier coupled to the receiver-side SiGe BiCMOS converter, and a receiver-side microstrip/waveguide interface coupled to the receiver-side GaAs pHEMT low noise amplifier.

BICMOS-based transceiver for millimeter wave frequency applications

GAAS/SIGE-BICMOS-based transceiver system-in-package for E-band frequency applications

Combined echo and crosstalk cancellation is provided. Frequency domain adaptive filters are used to remove or reduce the effects of echo and crosstalk for a multi-channel and full-duplex communications system. Data from each transmit channel is buffered and converted to the frequency domain. The frequency domain data is multiplied by crosstalk coefficients to obtain a frequency domain correction signal for each channel. Adaptation of the crosstalk coefficients is based on correlations between the error signals and the data from each of the transmit channels. A single frequency domain transform engine, such as a Fast Fourier Transform engine, is employed for all calculations to save power and area.

Combined echo and crosstalk cancellation

A method of digitally controlling a timing recovery loop to control jitter and reduce word-length in a recovered clock is provided. A timing error detector provides an output identifying the error sign. First and second randomizing digital attenuators provide first and second estimates of the phase error in a timing signal. A controller receives the first estimate and provides a signal to an NCO. An output from the NCO provides feedback to the error detector to complete a first order feedback loop, providing a first estimate phase error compensation. An integrator receives the second estimate and provides an output estimate for frequency offset of the timing signal that is received by the controller and the sign and magnitude of the integrated phase error are calibrated to provide a frequency offset. The controller determines a number of additional updates to the NCO required to minimize jitter and reduce word-length.

Method for frequency compensation in timing recovery

A 10GBASE-T clocking method that limits EMI and increases SNR, while reducing power and conserving chip space is provided. The method includes simultaneous clocking of transmitters in an analog front end of a 10 gigabit Ethernet. The method includes providing at least two channels to a 10GBase-T analog front end, where the channel has at least a transmitter port and a receiver port, and providing at least two phase interpreters to the analog front end, where each phase interpreter is dedicated to one receiver port. A central clock generator is disposed to distribute a transmit clock to the phase interpreters and to the transmitter ports, where the transmit clock is further provided to the receiver ports from the phase interpreters. Any clock delay between the clock generator and each channel is balanced and clock phases between the channels are matched.

Clock distribution for 10GBase-T analog front end

A low spur phase-locked loop (PLL) architecture is provided. A frequency-synthesizing PLL that includes a differential Kvco gain linearization circuit with adjustable DC offset is used to reduce clock jitter. The free-running oscillation frequency of the VCO of the PLL is centered near the desired frequency using programmable loads to minimize the required control voltage range. The PLL uses a differential architecture that includes a charge pump that compensates for variations in Kvco and a LC tank oscillator with differential controlled varactor. The differential PLL architecture demonstrates that the reference spur can be well controlled to below &#x2212;80 dBc.

Low spur phase-locked loop architecture

A finite impulse response filter having tap weight rotation is provided, where each tap has a corresponding coefficient selector. Each coefficient selector includes N coefficients, where N is the number of taps. Each coefficient selector provides one of its corresponding coefficients as an input to a multiplier. Each multiplier also receives an input from a triggered track and hold tap. The tap coefficients are selected according to the time delay since the corresponding track and hold tap was most recently triggered. In this manner, the tendency of multiplier gain nonuniformity to degrade filter operation in the presence of tap weight rotation is reduced. In another embodiment, an offset selector is provided, to reduce the tendency of component offsets to degrade filter operation in the presence of tap weight rotation.

Analog adaptive FIR filter having independent coefficient sets for each filter tap

A timing recovery system includes a phase locked loop with a variable bandwidth loop filter, several data dependent gain units, and three proportional paths with non-linear control. The system provides excellent jitter tolerance with a wide variation in data density and large amplitude jitter with a wide frequency range. The gain of both an included loop filter and a phase detector may be varied with both frequency and data density. Direct, unfiltered adjustments may be made to phase based on a received data pattern and phase error magnitude to reduce loop latency and provide temporary and immediate boost in the loop gain of the phase locked loop. Direct, unfiltered adjustments may also be made to phase based on the sign of the first differential of an accumulator output during long strings of zeros to help maintain tracking even with a very low data density.

Timing recovery with variable bandwidth phase locked loop and non-linear control paths

A line interface capable of connecting to a variety of transport mediums, each having a different impedance. The line interface comprises a programmable resistor. The programmable resistor along with an external resistor provide a range of resistor values which are used to substantially match the impedance requirements of the various transport mediums.

Apparatus and method for programmable line interface impedance matching

An adaptive slicer threshold generation system includes a first moving average filter to determine a first average value of a first binary signal. A second moving average filter is included to determine a second average value of a second binary signal. A combiner combines the first average value of the first binary signal and the second average value of the second binary signal to generate a combined output.

Apparatus and method to generate an adaptive slicer threshold for binary data

A receiver involved in high-speed data transmission includes a decision system. The decision system calculates a value of an input signal and holds the value as a tentative value. The decision system calculates an error value, amplifies the error value, and holds the amplified error value as a corrected value. The decision system determines whether the amplified error value is within a marginal range. The decision system also determines whether adjacent values to the value indicate the input signal was in transition from a positive to negative state, or a negative to positive state. If the amplified error values is within a marginal range and the input signal was in transition from a positive to negative state, or a negative to positive state, then the decision system overrides the tentative value with the corrected value.

Error correction method and apparatus for data transmission system

A method and system for performing integrated adjustable short-haul/long-haul time domain reflectometry (TDR). A TDR pulse count is set to a predetermined number. Next, a TDR pulse is transmitted through a cable. The width of the TDR pulse is a function of the multiplication of the TDR pulse count with the period of a TDR clock. It is then determined whether the TDR pulse has been reflected back. If the TDR pulse has not been reflected, the TDR pulse count is successively increased to successively increase the width of the transmitted TDR pulse until a reflection is detected&#x2014;indicating an open in the cable. Furthermore, it eliminates false detections of cable opens. Moreover, the system can be combined into a line interface unit (LIU) integrated circuit such that TDR functionality can be performed automatically without the use of a technician.

Integrated adjustable short-haul/long-haul time domain reflectometry

A frequency detector includes a slicer to receive and slice a phase error against a compare threshold value. The slicer generates a symbol based on the phase error sliced against the compare threshold value. A symbol counter is provided to increment a symbol count if the symbol generated is the same as a last symbol. A logic circuit compares the symbol count with a symbol count limit if the symbol is different from the last symbol. The logic circuit increments a high counter and clears a low counter if the symbol count is less than the symbol count limit. The logic circuit increments the low counter and clears the high counter if the symbol count is greater than the symbol count limit. A combinational logic circuit is provided to generate a high frequency jitter true signal or a high frequency jitter false signal based on at least one of the symbol count, the high counter, and the low counter.

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Sacramento, CA, United States of America

James Little