Harris Corporation

Conexant, Inc.

James Leroy Snell

Raymond F Cobb

Carl F Andren

Albert D Darby, Jr

Leonard Victor Lucas

A spread spectrum radio transceiver includes a high data rate baseband processor and a radio circuit connected thereto. The baseband processor preferably includes a modulator for spread spectrum phase shift keying (PSK) modulating information for transmission via the radio circuit. The modulator may include at least one modified Walsh code function encoder for encoding information according to a modified Walsh code for substantially reducing an average DC signal component to thereby enhance overall system performance when AC-coupling the received signal through at least one analog-to-digital converter to the demodulator. The demodulator is for spread spectrum PSK demodulating information received from the radio circuit. The modulator and demodulator are each preferably operable in one of a bi-phase PSK (BPSK) mode at a first data rate and a quadrature PSK (QPSK) mode at a second data rate. These formats may also be switched on-the-fly in the demodulator. Method aspects are also disclosed.

High data spread spectrum transceiver and associated methods

High data rate spread spectrum transceiver and associated methods

An interpolator includes: a first quadratic coefficient generator for generating a first coefficient set fitting a first quadratic equation to input samples y.sub.0, y.sub.1 and y.sub.2 at x.sub.-1, x.sub.0, and x.sub.1, respectively; a second quadratic coefficient generator for generating a second coefficient set fitting a second quadratic equation to input samples y.sub.1, y.sub.2 and y.sub.3 at x.sub.0, x.sub.1 and x.sub.2, respectively; a bi-quadratic coefficient generator for generating a bi-quadratic coefficient set based upon the first and second coefficient sets; and an output circuit for generating an interpolated value for between x.sub.0 and x.sub.1 based upon the bi-quadratic coefficient set. The bi-quadratic generator preferably generates the bi-quadratic coefficient set based upon an average of the first and second coefficient sets. Accordingly, the bi-quadratic coefficient set of b.sub.0, b.sub.1 and b.sub.2 is given by b.sub.0 =y.sub.1, b.sub.1 =(-y.sub.3 +5y.sub.2 -3y.sub.1 -y.sub.0)/4, and b.sub.2 =(y.sub.3 -y.sub.2 -y.sub.1 +y.sub.0)/4. The interpolated value y(.DELTA.x) is equal to b.sub.0 +.DELTA.x(b.sub.1 +.DELTA.xb.sub.2). Polynomial coefficient generators may be used for polynomial equations of orders higher than two as in the quadratic equations. In addition, method aspects of the invention are also disclosed.

Interpolator using a plurality of polynomial equations and associated

A re-sampling circuit includes a poly-phase finite impulse response (FIR) interpolator; a polynomial interpolator having a sample input connected to a sample output of the poly-phase FIR interpolator; and a numerically controlled oscillator (NCO) having an output partitioned into: Nc integer bits connected to a control input of the FIR interpolator, and Nf fractional bits connected to a control input of the polynomial interpolator. The circuit may also include a reference clock for generating a reference clock signal. The NCO preferably further comprises a sample clock generator for generating a sample clock signal based on the reference clock signal, and the FIR interpolator further has a sample clock input for receiving the sample clock signal from the sample clock generator. In addition, the polynomial interpolator also preferably has an input for clocking output samples therefrom that is connected to the reference clock so that output samples from the polynomial interpolator are clocked out based upon the reference clock signal. The re-sampling circuit may be used in a modulator, for example, also including one or more mixers.

Re-sampling circuit and modulator using same

A technique for deriving a phase reference for PSK demodulation uses the absolute values of phase vectors as they are received to establish a reference with which the individual phase vectors are compared for data demodulation. Over some span of N successively received signals (phase vectors), the received phase vectors are successively analyzed to derive a hypothetical reference phase vector with which the vector symbols are to subsequently compared for data demodulation. The symbol values are temporarily buffered as they are received. As each phase vector is received, all possible (i.e. M-ary) phase values, referenced to the value of the received phase vector, are compared to a stored reference. Each of these M-ary possible phase values is vector-summed with the stored reference and the resulting vector sum having the largest magnitude is then substituted for the stored reference and is used by the next received vector symbol to further refine the reference vector. This process is carried out successively for each of the received phase vector of the N-symbol span, at the completion of which the successively refined value of the stored reference vector is used to demodulate the previously received and buffered N symbols of the span of interest.

M-phase PSK vector processor demodulator

In a communication system, a signal detection and acquisition system, which is capable of locating and phase-locking onto a narrow-band signal in a large frequency uncertainty region in a short period of time, employs the following series of operations:

Sequential detection system

A carrier recovery scheme for a PSK demodulator through which side locking onto an interference-created sideband is avoided includes a hard-limited upstream of a phase-locked loop which removes jammer-induced AM from the input signal. As the loop sweeps through the frequency range of interest, a lock detector, coupled to the phase-locked loop will lock onto or acquire only the true carrier and thereby enable demodulation of the PSK information signal. In a digital implementation of the invention, received PSK input signals are converted into digital format by a multi-level quantizer, after being down-converted to an IF signal and subjected to gain control. The output of the quantizer may be a multi-bit, parallel word indicative of the changing amplitude of the IF signal which is to be sampled at the receiver sampling rate and converted into a digitally encoded representation of a received IF signal sample. Successive digitally encoded samples are coupled through matched in-phase (I) and quadrature (Q) channel filters and applied to a phase-locked loop. The phase-locked loop is, in turn, coupled to a lock detector which controls the operation of the hard-limiter. The phase-locked loop is also coupled to the quantizer to control the rate at which quantized input signals are sampled. Prior to acquiring the carrier, the output of the lock detector is such that the quantizer effectively hard-limits the PSK input to one of two levels, so that it is essentially polarity sensitive, rather than both polarity and magnitude sensitive. Once the carrier has been acquired, the lock detector removes the hard-limiting action of the quantizer and causes the quantizer to operate in its normal multi-level mode. Although removal of the hard-limiting action of the quantizer permits AM sidebands to return, the loop has already locked onto the true carrier, so that the sidebands will not be swept to cause false locking.

Growing community of inventors

Palm Bay, FL, United States of America

James Leroy Snell