Nvidia Corporation

3dlabs Inc., Ltd.

Intergraph Corporation

James Leroy Deming

Jerome Francis Duluk, Jr

Mark Hairgrove

Cameron Buschardt

John Mashey

Brian Matthew Fahs

Samuel Hammond Duncan

Lucien Dunning

Dale L Kirkland

Chenghuan Jia

Steven James Heinrich

Timothy John Purcell

Clifford A Whitmore

Matt E Buckelew

Robert T George

Arvind Gopalakrishnan

Mark Allen Mosley

Jonathon Stuart Ramsey Evans

Sherry Cheung

Steven E Molnar

Wishwesh Anil Gandhi

Gregory Scott Palmer

Shailendra Singh

Alan Menezes

Manas Mandal

Praveen Joginipally

Pranav Vaidya

Feiqi Su

Lacky V Shah

Stewart G Carlton

Timothy S Johnson

Nick Barrow-Williams

Jay Gupta

William Craig McKnight

Michael S Farmer

Eric Rock

James M Van Dyke

Jay Huang

Jonathon Stuart Ramsay Evans

Sonata Gale Wen

Henry Packard Moreton

David Brian Glasco

Jeffrey A Bolz

Rui Manuel Bastos

Yury Y Uralsky

Patrick Richard Brown

Parthasarathy Sriram

Andrew J Tao

Colyn Scott Case

Michael Wasserman

Jeff S Ford

Christian Amsinck

Jonathan J Dunaisky

Poornachandra Rao

Franciscus W Sijstermans

Michael Potter

Michael Asbury Woodmansee

Jeffrey M Smith

Jeffrey J Holt

David W Young

Amanpreet Grewal

Emmett M Kilgrariff

Gilberto Contreras

A parallel processing unit (PPU), operating in a traditional processing environment or in a virtualized processing environment, can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

Techniques for configuring a processor to function as multiple, separate processors in a virtualized environment

A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

Techniques for configuring a processor to function as multiple, separate processors

A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

Fault buffer for tracking page faults in unified virtual memory system

Techniques for reconfiguring partitions in a parallel processing system

Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.

PCIe traffic tracking hardware in a unified virtual memory system

One embodiment of the present invention includes a memory management unit (MMU) that is configured to efficiently process requests to access memory that includes protected regions. Upon receiving an initial request via a virtual address (VA), the MMU translates the VA to a physical address (PA) based on page table entries (PTEs) and gates the response based on page-specific secure state information. To thwart software-based attempts to illicitly access the protected regions, the secure state information is not stored in page tables. However, to expedite subsequent requests, after the MMU identifies the PTE and the corresponding secure state information, the MMU stores both the PTE and the secure state information as a cache line in a translation lookaside buffer. Advantageously, the disclosed embodiments protect data in the protected regions from security risks associated with software-based protection schemes without incurring the performance degradation associated with hardware-based 'carve-out' memory protection schemes.

Storing secure state information in translation lookaside buffer cache lines

Fault buffer for resolving page faults in unified virtual memory system

One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

Microcontroller for memory management unit

A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

Efficient memory virtualization in multi-threaded processing units

Migration scheme for unified virtual memory system

Growing community of inventors

Madison, AL, United States of America

James Leroy Deming