Texas Instruments Corporation

Burr-brown Corporation

Texas Instruments Incorporated Deutschland, Gmbh

James Lee Todsen

Timothy V Kalthoff

Ka Yin Leung

Binan Wang

Shang-Yuan Chuang

Abdullah Yilmaz

Caspar Petrus Laurentius Van Vroonhoven

Brian David Johnson

Binling Zhou

Self-monitoring reset circuitry is presented for use in analog-to-digital converters and other modulator circuitry with capacitively coupled isolation barriers in which the modulator output data is monitored for inactivity by a reset circuit synchronized to the modulator clock, and extra pulses are selectively introduced into the data prior to transmission across the isolation barrier if no modulator state changes occur within a predetermined number of clock cycles to provide a predictable data output value for each end of the analog input range and to reset the output to the correct state in situations where transient noise toggles the output and the modulator output is static.

Isolated modulator circuit with synchronized pulse generator for self-monitoring reset with capacitively-coupled isolation barrier

A bottom die and a top die stacked on the bottom die are configured to provide a daisy chain function. Both die include an input/output function control bonding pad (G), a first bonding pad (C) controllable to function as either an input or an output, and a second bonding pad (E) controllable to function as either an output or an electrically floating pad in response to a corresponding input/output function control signal. The top die () is stacked on the bottom die () and the first bonding pad (C) of the bottom die () is wire bonded to the first bonding pad (C) of the top die (). A first reference voltage (VDD) on the function control bonding pad of the bottom die configures its first bonding pad as an output and its second bonding pad as electrically floating, and a second reference voltage (VSS) on the function control bonding pad of the top die configures its first bonding pad as an input and its second bonding pad as an output, to thereby provide the daisy chain function.

Daisy chaining of serial I/O interface on stacking devices

A technique and circuit is provided for facilitating a faster settling time for a digital filter for use with an analog-to-digital converter. An exemplary technique utilizes a composite filter for a faster settling, lower noise resolution filter in a parallel configuration with a slower settling, higher noise resolution filter. As a result, valid data can be received faster for processing by the analog-to-digital converter. In addition, a composite digital filter circuit can include a three filter configuration including a fast-settling, low resolution first filter, a slower-settling, higher resolution second filter, and an even slower-settling, even higher resolution third filter, each of the filters configured in a parallel arrangement. Additional or fewer filters can also be provided. Moreover, the gain of each filter path can be suitably matched to the gain of any other filter path in the digital filter circuit to provide a filter output having an equalized gain regardless of the filter path selected. For example, a filter path can be suitably configured with a multiplier component such that an equalized gain can be realized for each filter path. In addition, the various filters of the digital filter circuit can be configured within the parallel arrangement to provide reduce layout requirements through the sharing of components. For example, a second filter can share at least two integrators with the third filter, and the first filter can share at least one integrator with the third filter. Further, the digital filter can be suitably configured for operation in various industrial applications. For example, the first filter can be suitably configured with a notch filter configured to replace the first, third and other odd harmonic notches of the first filter.

Fast-settling digital filter and method for analog-to-digital converters

An analog-to-digital converter ( ) includes a high order delta sigma modulator followed by a decimation filter. A monitor circuit ( )coupled to the output of the delta sigma modulator operates to reset its integrators if an unstable condition is detected on the output. The monitor circuit produces first and second jamming signals in response to either a detected overvoltage or undervoltage of the delta sigma modulator input. A logic circuit (SW ) includes a data input coupled to the output of the delta sigma modulator and a data output ( ) that jams the input of digital filter ( ) with &ldquo;1&rdquo; s or &ldquo;0&rdquo; s in response to the first or second jamming signal, respectively, to ensure a correct (&plus;) or (&minus;) full scale decimation filter output.

Method and circuit for jamming digital filter while resetting delta sigma modulator

An input buffer circuit for use with an analog-to-digital converter is provided. The input buffer circuit comprises a first amplifier configured with a second amplifier to improve the overall gain of the input buffer circuit. The first amplifier comprises a differential pair of transistors configured with a second pair of transistors comprising a current mirror arrangement, wherein one of the differential pair of transistors of the first amplifier is configured in a diode-connected arrangement to provide a first feedback loop, while the second amplifier comprises a differential pair of transistors configured with another pair of transistors also comprising a current mirror arrangement, with the second amplifier and the current mirror arrangement of the first amplifier comprising a second feedback loop. Further, the first amplifier is configured such that the differential pair of transistors comprise different sized transistor devices, thus creating an offset voltage which permits the input voltage to swing close to ground, and which maintains the output voltage at voltage level higher than the input voltage by the amount of the offset voltage.

Input buffer for analog-to-digital convertor

A method and apparatus for performing gain calibration of an analog to digital converter is provided. During a calibration mode, an input sampling circuit comprised of multiple branches can be configured to provide a calibration mode gain of one. The analog-to-digital converter selects one of the parallel capacitor input sampling branches and repetitively samples the whole charge associated with the calibration voltage signal. This sampling step is repeated for each input sampling branch that is used during normal operation mode. The results of the sampling of the branches may be suitably averaged to create a gain calibration coefficient that is representative of and accounts for sampling variations between the input branches.

Apparatus and method for gain calibration technique for analog-to-digital converter

A programmable integrated circuit capacitor array includes a plurality of binarily weighted capacitors (16) and a plurality of switches (18) selectively coupling the capacitors in parallel between first and second terminals. A control circuit (10) responds to a plurality of capacitance selection inputs (CS0,1,2) in conjunction with a plurality of trim inputs (TR0,1) and a sign input (TRS) to produce a plurality of selection signals (SEL0,1 . . . 7) on control electrodes of the switches to couple one or more of the capacitors and thereby provide an accurate value of the desired capacitance between the first and second terminals despite any manufacturing deviations in capacitance per unit area.

Capacitor array having user-adjustable, manufacturer-trimmable

An integrating circuit includes an operational amplifier and an integrating capacitor which is decoupled from the output of the operational amplifier and precharged to a positive reference voltage before each integration cycle. During each integration cycle the operational amplifier output decreases from the reference voltage toward but not below ground. This allows the operational amplifier to be included as a front-end integrator to a delta-sigma analog-to-digital converter that is powered only by a single power supply. In the described embodiment, the output is coupled to an input of an auto-zeroing stage which provides negative feedback to stabilize the operational amplifier when the integrating capacitor is disconnected during precharging and a bandwidth control input which couples a larger compensation capacitance to reduce the bandwidth during integration to reduce RMS noise. In the described embodiment, a correlated double sampling capacitor is discharged to zero while the integrating capacitor is precharged and kT/C error and charge injection error voltages of opposite polarity are stored on both the integrating capacitor and the correlated double sampling capacitor. The correlated double sampling capacitor is switched into the feedback of the operational amplifier in series with the integrating capacitor to automatically cancel the error voltages and present a more accurate input to the delta-sigma analog-to-digital converter.

Growing community of inventors

Tucson, AZ, United States of America

James Lee Todsen