International Business Machines Corporation

Skhynix Inc.

James Lee Hafner

Steven Robert Hetzler

Mario Blaum

Aayush Gupta

Mohit Saxena

Krishnakumar Rao Surugucchi

Binny Sher Gill

Wendy Ann Belluomini

Paul Stuart Williamson

Melissa Wiltsey O'Mara

Karl Allen Nielsen

Robert Akira Kubo

Tarun Thakur

David Frank Mannenbach

David Ray Kahler

Lokesh M Gupta

Michael T Benhase

Bulent Abali

David Darden Chambliss

Martin Aureliano Hassner

Daniel Felix Smith

Mohammad Banikazemi

Charles Edwin Cox

John Anthony Tomlin

Tapas Kanungo

Jeffrey R Hartline

Carl Evan Jones

David Allan Pease

Colin George Harrison

Dan Edward Poff

Veera W Deenadhayalan

Allan James Schurr

Venu Nayar

James A O'Conner

Mingyuan Xia

Timothy Joseph Chainer

Nimrod Megiddo

Myron Dale Flickner

James A O'Connor

Brian Dennis McKean

Donald Roman Humlicek

Douglas William Dewey

Barry Marshall Trager

James Christopher Wyllie

Arvind M Patel

Shmuel Winograd

Kevin Lee Kidney

Larry Lynn Williams

Richard B Stelmach

Assaf Nitzan

Edi Shmueli

Theresa Lynn Segura

Ronald Ambrosio

Erica Haefner Ferro

Mark William Trekell

Krishnakumar S Rao

Ralph Koetter

Dulce Beatriz Ponceleon

Bret S Weber

Maohua Lu

Kenneth F Day, Iii

Prashant Pandey

Wilfred Edmund Plouffe, Jr

Eliezer Upfal

Deepak R Kenchammana-Hosekote

Leo Shyh-Wei Luan

Richard Francis Freitas

Omer Ahmed Zaki

John E Bish

Eyal Lotem

Marc Thadeus Roskow

Daniel Edward Poff

Veera A Deenadhayalan

Krishankumar Rao Surugucchi

Eyal Lotern

Garth R Goodson

Veera c/o Ibm Uk Limited Intellectual Property Law Deenadhayalan

A method for memory page erasure-correcting property generation in a storage array includes dividing data into multiple stripes for storage in a storage array including multiple storage devices with a topology of a hypercube of a dimension t&#x2265;3. The storage devices in same hypercubes of dimension t&#x2212;1 including the hypercube of dimension t have even parity. An intersection of two non-parallel planes in the hypercube topology is a line, and each point along a line is a storage device in the storage array. Erasure-correcting properties are generated for the data using three nested codes, wherein a first nested code has even parity over planes of class 0, 1 and 2, a second nested code has a first global parity, and a third nested code has a second global parity and a third global parity.

Erased memory page reconstruction using distributed coding for multiple dimensional parities

In one embodiment, a computer-implemented method includes selecting a cache block descriptor (CBD) from amongst a plurality of CBDs stored to a cache storage device to defragment based on a determination of utilization of a particular fine block descriptor (FBD) having a first size that is allocated to the selected CBD. The cache storage device includes a free pool of FBDs having various sizes that is available for use in the plurality of CBDs. Also, the particular FBD having the first size has a lowest availability in the free pool of FBDs. Other methods, systems, and computer program products are described in accordance with additional embodiments.

Reducing defragmentation in a multi-grained writeback cache

An apparatus comprises a storage controller coupled to at least one multi-region storage device. The at least one multi-region storage device comprises two or more storage regions, the two or more storage regions comprising a first storage region associated with a first set of failure characteristics and at least a second storage region associated with a second set of failure characteristics different than the first set of failure characteristics. The storage controller is configured to replicate in the second storage region at least a portion of data that is stored in the first storage region.

Storing data in multi-region storage devices

Embodiments relate to host-side cache migration. An aspect is a method that includes determining pre-fetch hints associated with a source cache that is local to a source host machine. The source cache includes pages of cache data for a virtual machine. The pre-fetch hints are sent to a pre-fetch planner to create a pre-fetch plan. The pre-fetch hints are sent based on migration of the virtual machine to a target host machine including a target cache that is local. At the source host machine, a cache migration request is received based on the pre-fetch plan. A first subset of the pages is sent from the source cache through a host-to-host communication channel to the target cache based on the cache migration request. A second subset of the pages is sent from the source cache through a host-storage communication channel to a shared storage to be relayed to the target cache.

Host-side cache migration

Embodiments relate to a system with multiple erasure codes, and selecting and encoding for a write file with one of the codes to mitigate costs associated with storage recovery. The codes include a fast recovery code for frequently accessed data and a higher storage efficiency code for less frequently accessed data. State data is tracked to ascertain frequency of access to the file. One of the erasure codes is dynamically selected based on the tracked data, with the focus of the code select to lower recovery costs, and the data is encoded with the selected erasure code. Accordingly, the original coding of the write file is subject to change based on the tracked state data.

Multiple erasure codes for distributed storage

A method for memory page erasure reconstruction in a storage array includes dividing data into multiple stripes for storage in a storage array including multiple storage devices with a topology of a hypercube of a dimension t&#x2265;3. The storage devices in same hypercubes of dimension t&#x2212;1 including the hypercube of dimension t have even parity. An intersection of two non-parallel planes in the hypercube topology is a line, and each point along a line is a storage device in the storage array. A reconstructor processor reconstructs erased data for erased memory pages from non-erased data in the storage array by using parities in at least three dimensions based on the hypercube topology of the storage devices.

In one embodiment, a system includes a cache storage device, a back-end storage device, and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive indication of failure of a primary cache server at a secondary cache server, the primary and secondary cache servers being configured to manage read requests and write requests for the back-end storage device. The logic is also configured to set the secondary cache server to a by-pass mode for read requests directed to any portions of the back-end storage device managed by the primary cache server prior to the failure. Moreover, the logic is configured to read an index of cache block descriptors (CBDs) managed by the primary cache server prior to the failure into a memory of the secondary cache server.

Instant recovery in a multi-grained caching framework

A method for distributed coding in a storage array is presented. The method includes dividing data into multiple stripes for storage in a storage array including storage devices with a topology of a hypercube of a dimension t&#x2265;3. The storage devices in same hypercubes of dimension t&#x2212;1 including the hypercube of a dimension t have even parity. Global parities are added to the hypercube such that a minimum distance of a code is enhanced.

Distributed coding for multiple dimensional parities

Embodiments relate to dynamically selecting an erasure code. State data is tracked to ascertain frequency of file access. One of at least two erasure codes are selected based on the tracked state data in order to lower data recovery cost. The erasure code may be selected as either a product code or a local reconstruction code. Each erasure code includes a mode that is either a fast code or a compact code. The fast code features a low recovery cost and the compact code features a low storage overhead for less frequently accessed data. Data is encoded with one of the selected erasure codes and one of the modes of the selected erasure code. Data blocks are dynamically converted between the fast and compact codes of the selected erasure code responsive to a workload change.

In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive a plurality of access requests for data in the cache storage device, each request being directed to data in a common cache block descriptor (CBD). The CBD stores metadata corresponding to a storage location of the data in the cache storage device. The logic is also configured to update a request queue to reflect each access request from the plurality of access requests in an order in which individual access requests were received. Moreover, the logic is configured to delay at least some overlapping access requests.

Supporting concurrent operations at fine granularity in a caching framework

In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to select a cache block descriptor (CBD) from amongst a plurality of CBDs, the selected CBD including indications of being fragmented in the cache storage device. The logic is also configured to determine whether to defragment the selected CBD. Moreover, the logic is configured to defragment the selected CBD on the cache storage device in response to a decision to defragment the selected CBD.

In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive a write request including data to be written to the cache storage device. The logic is also configured to determine a size of the write request. Moreover, the logic is configured to select a chunk size from among a plurality of chunk sizes designated for storing data in the cache storage device. In addition, the logic is configured to allocate a fine block descriptor (FBD) having the selected chunk size to the write request.

Space allocation in a multi-grained writeback cache

In one embodiment, a system includes a back-end storage device, a cache storage device, and a processor and logic integrated with and/or executable by the processor. The logic is configured to store data to the cache storage device using fine block descriptors (FBDs) configured for fine-grained mapping of variable-size cache allocations. The logic is also configured to store data to the back-end storage device using cache block descriptors (CBDs) configured for coarse-grained mapping of large blocks of data. At least some FBDs are smaller in size than any of the CBDs, and all FBDs are equal to or smaller in size than any of the CBDs.

Scalable metadata management in a multi-grained caching framework

A computer implemented method, apparatus, and computer program product for generating an energy transaction plan to manage an electric vehicle charging transaction. The energy transaction planner identifies an electric vehicle associated with a charging station and a set of principals associated with a charging transaction for the electric vehicle. The charging transaction is a transaction associated with at least one of charging the electric vehicle, storing electric power in an electric storage mechanism associated with the electric vehicle, and de-charging the electric vehicle. The energy transaction planner receives charging transaction information. The charging transaction information comprises requirements, constraints, and preferences applicable to the charging transaction. The energy transaction planner generates an energy transaction plan based on the charging transaction information. The energy transaction plan comprises terms for governing all aspects of the charging transaction.

Generating energy transaction plans

Growing community of inventors

San Jose, CA, United States of America

James Lee Hafner