Linear Technology Corporation

Intersil Corporation

James Lee Brubaker

William C Rempfer

Hassan Malik

Patrick Philip Copley

Florin Alexandru Oprescu

Ziya G Boyacigiller

Victor Paul Schrader

Jerome C Zis

A differential current steering (CS) circuit uses feedback from the differential output nodes A and B to cause current steering devices (e.g., MOSFETs) to effectively exhibit an infinite output impedance when conducting. Therefore, the signal on the output nodes A or B does not significantly change the voltage at the common node, This is particularly useful when the differential output nodes are connected to differential output buses in a digital-to-analog converter. The circuit dynamically cancels, though feedback, the signal induced at the common node by the signal present at the 'steered' output node. Therefore, the CS circuit effectively presents an infinite output impedance between the common node and the output nodes. In some cases, it may be desirable to not create a substantially infinite output impedance for the CS circuit but control the impedance to a predefined level to counter other distortions in the system.

Current steering circuit with feedback

A switch signal generator circuit that may form part of a digital to analog converter is provided. The switch signal generator circuit may include a first switch that controls a high reference gate voltage. The high reference gate voltage may provide the ON state voltage for a plurality of switches that control the coupling of a high reference voltage to the digital to analog converter. The switch signal generator circuit may include a second switch that controls a low reference gate voltage. The low reference gate voltage may provide the ON state voltage for a plurality of switches that control the coupling of a low reference voltage to the digital to analog converter. The switch signal generator circuit may also include a resistor. In one embodiment of the invention, a current conducted by the first switch and/or a current conducted by the second switch may each be proportional to a current conducted by the resistor. One of the switches in the switch generator circuit may be a P channel switch. One may be an N channel switch. In one embodiment of the invention, current conducted by the first switch may be proportional to the current conducted by the second switch. Also the current conducted by the first switch may be proportional to temperature.

Systems and methods for switch resistance control in digital to analog converters (DACs)

Digital to analog converter circuits and methods are provided for producing an analog output voltage indicative of a digital input signal with at least partial insensitivity to error gradients. Described are split-core resistive elements, which include a plurality of one-dimensional or multi-dimensional resistive strings, that may be used to reduce or substantially eliminate the effects that error gradients have on the linearity of the analog output voltages of a resistive string or interpolating amplifier DACs. The resistor strings that make up the split-core resistive elements are configured in such a manner that combining respective output voltages from each of the resistor strings results in an analog output voltage that is at least partially insensitive to the effects of error gradients.

Gradient insensitive split-core digital to analog converter

A trimdac circuit for adjusting the output of a digital-to-analog converter (DAC) is provided. The trimdac may be used to adjust a plurality of resistor segments in the DAC. The trimdac may include a programmable Read Only Memory (ROM) or other suitable memory device. The ROM may include a plurality of multi-bit digital words. Each of the multi-bit digital words may control a plurality, and most preferably a pair of variable resistance circuits. Each of the pair of variable resistance circuits may adjust a resistor segment of the DAC.

Systems and methods for providing compact digitally controlled trim of multi-segment circuits

A digital to analog converter that receives a digital signal and that converts the digital signal to an analog input signal is provided. The converter may include a group of most significant bits. The group is decoded to drive a plurality of equivalent most significant segments. The converter may also include a second group of bits. The second group is decoded to drive a second plurality of equivalent segments.

Systems and methods for reducing transient errors on digital to analog converters (DACs) deglitcher

A signal processor circuit that buffers a ground-referred, signal-dependent, current. A ground-referred node in the circuit is preferably maintained at a ground level. The ground-referred, signal-dependent, current is preferably buffered such that the ground-referred node is preferably maintained at a ground level independent of changes to the ground-referred, signal-dependent, current.

Circuits, systems, and methods for signal processors that buffer a signal dependent current

A signal processor circuit which receives an input signal and two control words and is programmable to vary the level and the output voltage range of the output signal is provided. The signal processor includes a converter circuit and a level circuit which provide the output circuit with intermediate signals based on input control signals, e.g., input digital words. The output circuit receives an additional control signal and the intermediate signals and is programmable to modify the output voltage range and level of the output signal based on the additional control signal, e.g., a digital word.

Programmable configuration, level and output voltage range circuits and methods for signal processors

A switch impedance insensitive signal processor is provided. A signal processor according to the present invention overcomes the problem of switch impedance by adding an individual buffer, e.g. a unity-gain amplifier, between the switch and the processor portion of the circuit. The buffer isolates the signal processor from the switch impedance.

Signal processor

A voltage interpolation circuit for a digital-to-analog converter comprises a differential amplifier with composite input devices, each of which is composed of multiple active subtransistors. Interpolation is effected between a first voltage and a second voltage by selectively connecting the gates of the active subtransistors in one of the composite devices to either the first voltage or the second voltage. Each active subtransistor operates in conjunction with a voltage-controlled degeneration subtransistor to form a functional subtransistor pair. Using the nonlinear conductance characteristic of MOS devices operated in the triode region, the transconductance of each functional subtransistor pair is modulated in such a way as to be made relatively insensitive to changes in effective gate-to-source voltage V.sub.GS ', so that the interpolation circuit produces equally sized interpolated voltage steps at an analog output.

Interpolation circuit for digital-to-analog converter

A high accuracy monolithic digital to analog converter (DAC) which employs an EPROM controlled correction DAC to correct for errors in the output of a primary DAC. The correction DAC empolys a non-binary bit weighting which permits the use of low accuracy components in the fabrication of the correction DAC. The output of the primary DAC is skewed so that the required correction is always in a single direction, thereby eliminating the need for a constant offset generator. Resistors necessary for bipolar operation are included on the chip, thereby eliminating the need for connection of any external resistors to achieve such operation.

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Milpitas, CA, United States of America

James Lee Brubaker