Hewlett-packard Development Company, L.P.

Hewlett-packard Company

James Lawrence White

James J deBlanc

Anthony Joseph Benson

David Dickey

Timothy M Anderson

Dovard K Howard

Carl R Haynie

William Gordon Hooper, Iii

William G Hooper Iii

William G Iii Hooper

A connection architecture for a data-storage system may include: a connection-plane structure; a data-storage module attached to, and drawing power from, the connection-plane structure; an input/output (I/O) module attached to, and drawing power from, the connection-plane structure; and wireless means for exchanging data wirelessly between the data-storage module and the I/O module.

Data-storage system having a wireless connection architecture for wireless data exchange between modules

A backplane apparatus for an electronic device enclosure includes a common bus comprising a plurality of signal lines, each signal line having a current limiting element, RA. Isolation circuitry is provided for electrically coupling each of the plurality of signal lines of the common bus to a corresponding plurality of signal lines of the electronic device to enable signal communication between the common bus and the electronic device through the isolation circuitry. In one embodiment, the backplane apparatus further comprises connectors to enable removably attaching the electronic devices such as disk drives. In one embodiment, the isolation circuitry coupling each signal line of the common bus to the connector comprises an inline resistor, RD. The isolation circuitry associated with some of the signal lines may include pull up resistors. The values of RA and RD are selected to ensure that the common bus meets pre-determined current and voltage requirements so that the common bus can change states even if one or more of the devices fail by shorting to ground.

Fault tolerant bus for highly available storage enclosure

A self-test method and system for facilitating reliable and fault-tolerant operation of a multi-peripheral-device enclosure for use in high-availability computer systems. The reliable and fault-tolerant multi-peripheral-device enclosure uses a three-tiered port bypass control strategy for diagnosing and isolating malfunctioning peripheral devices within the multi-peripheral-device enclosure, and uses a similar a three-tiered port bypass control strategy for isolation of the entire multi-peripheral-device enclosure from a communications medium that interconnects the multi-peripheral-device enclosure with one or more host computers. This three-tiered port bypass control strategy is employed by a self-test routine to isolate the multi-peripheral-device enclosure from external processing elements in order to test peripheral devices and other components within the multi-peripheral-device enclosure, and to isolate any detected defective or malfunctioning components.

Private arbitrated loop self-test management for a fibre channel storage enclosure

Apparatus for connecting a plurality of electronic devices with corresponding backplanes to improve reliability of accessing the devices are described. In one embodiment, the apparatus includes first and second backplanes having connectors for at least one device. A device having a plurality of data paths has a first data path coupled to a data path connector of the first backplane. A second data path of the device is coupled to a data path connector of the second backplane. Alternatively, a Y-adapter is used to connect a single data path device to data path connectors of distinct backplanes. In various embodiments, the backplanes lie in a common plane. Alternatively, the backplanes lie in distinct parallel planes.

Electronic device backplane interconnect method and apparatus

A communication system has multiple communication buses and multiple bus controller cards each supplying at least two independent channels of communication between one or more hosts and the communication buses. One of the controller cards is designated as a primary controller card for managing the communication buses and resetting the communication buses such that if a controller card is inserted to or removed from the system then the buses are reset.

Bus reset management by a primary controller card of multiple controller cards

A communication system with a plurality of interface slots includes control logic for determining and designating the status of one or more controller cards inserted in one of the slots such that: a controller card is designated as the primary card if it is inserted in an interface slot while the other slots are empty; a controller card in an interface slot with primary status retains its primary status while other controller cards are added or removed from the system; a controller card in an interface slot with a non-primary status assumes primary status if the controller card with non-primary status is plugged in a slot that after a power interruption is designated as the slot to assume primary status, or the controller card with primary status is removed from the system.

Communication bus controller including designation of primary and secondary status according to slot position

A device includes a first SCSI bus, a second SCSI bus, a first bus controller slot, a second bus controller slot and a bus controller in one of the first bus controller slot and the second bus controller slot. The bus controller includes reset circuitry for generating a SCSI bus reset signal. The SCSI bus reset signal being used to reset the first SCSI bus when the bus controller is in the first bus controller slot and the first SCSI bus is isolated from the second SCSI bus. The SCSI bus reset signal being used to reset the second SCSI bus when the bus controller is in the second bus controller slot and the first SCSI bus is isolated from the second SCSI bus. The SCSI bus reset signal is to reset both the first SCSI bus and the second SCSI bus when the first SCSI bus and the second SCSI bus are bridged and one of the following conditions is met: the bus controller is in the first bus controller slot, or the bus controller is in the second bus controller slot and the first bus controller slot is empty.

Management of resets for interdependent dual small computer standard interface (SCSI) bus controller

Method and system for enhancing the reliability of an available storage subsystem. Data storage units are equipped with a number of I/O controller-card adaptors that mate with complementary adaptors affixed to a number of redundant I/O controller cards. The data storage devices plug directly into I/O controller cards and receive all data, control signals, and power equally from the I/O controller cards, eliminating the need for a midplane circuit card.

Method and system for directly interconnecting storage devices to controller cards within a highly available storage system

A method and system for facilitating reliable and fault-tolerant operation of a multi-peripheral-device enclosure for use in high-availability computer systems by redundant interconnection of redundant processors within the multi-peripheral-device enclosure. The redundant interconnection removes a potential single point of failure, and allows the redundant processors to share in control of other components within the multi-peripheral-device enclosure. The multi-peripheral-device enclosure can recover from failure of all but one of the redundant processors, as well as failure in all but one of the redundant busses used to interconnect the two processors.

Peer controller management in a dual controller fibre channel storage enclosure

A reliable and fault-tolerant multi-peripheral-device enclosure for use in high-availability computer systems. The reliable and fault-tolerant multi-peripheral-device enclosure uses a three-tiered port bypass control strategy for diagnosing and isolating malfunctioning peripheral devices within the multi-peripheral-device enclosure, and uses a similar a three-tiered port bypass control strategy for isolation of the entire multi-peripheral-device enclosure from a communications medium that interconnects the multi-peripheral-device enclosure with one or more host computers.

Method and system for enhancing fibre channel loop resiliency for a mass storage enclosure by increasing component redundancy and using shunt elements and intelligent bypass management

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Roseville, CA, United States of America

James Lawrence White