Raytheon Company

James L Vorhaus

Robert A Pucel

Mark S Durschlag

Robert W Bierig

A n-bit digitally controlled phase shifter for controlling the phase of an applied signal over the range of 0.degree. to 360.degree. includes n, cascade interconnected phase shifter stages. Each phase shifter stage is formed on a semi-insulating substrate having a pair of field effect transistors and a pair of transmission lines formed thereon. Each field effect transistor (FET), includes a pair of gate electrodes, a drain electrode, and a source electrode, connected in a common (grounded) source configuration. Each transmission line is coupled between a corresponding one of the drain electrodes and a common output port. The lengths of the transmission lines are selected to provide two paths having an electrical pathlength corresponding to a phase shift of .phi..sub.1 or a phase shift of .phi..sub.1 +.DELTA..phi..sub.1 where .DELTA..phi..sub.i is the phase shift increment of the i.sup.th stage. A first one of the gate electrodes of each field effect transistor is fed by the applied signal. A pair of control signals representative of one of the bits, and its compliment, is fed to the second gate electrodes of the field effect transistors, and is used to selectively couple the applied signal to one of the drain electrodes of such field effect transistors. The phase of the applied signal is shifted by propagation through the transmission line selected through control signals. Each one of the n stages, has a predetermined electrical pathlength difference for providing a selected phase shift increment (.DELTA..phi..sub.i).

N-bit digitally controlled phase shifter

Lumped passive components including a capacitor having a silicon nitride dielectric, a tantalum film resistor, and a capacitor having a tantalum oxide dielectric are formed on a semi-insulating substrate by first providing an insulating layer, here of silicon nitride, over the substrate and metal contacts having previously been formed on such substrate. The metal contacts provide a first plate for each one of such capacitors. A tantalum layer is reactively sputtered on the insulating layer, and a protective masking layer is next provided on such tantalum layer. An area where the anodized tantalum capacitor is to be formed is then opened in the protective masking layer over a selected one of the metal contacts. A portion of the tantalum is anodized in such area to form an area of a tantalum oxide (Ta.sub.2 O.sub.5). The area where the tantalum oxide is formed is confined generally to the area in the tantalum layer over the contact. The masking layer is removed and a second masking layer is patterned to provide an etching mask used to etch the tantalum layer to define each one of such capacitors, and to provide a strip of tantalum, defining a region for said tantalum resistor. Top metal contacts are then provided aligned with the first set of such contacts, and thus providing a second metal plate of the anodized tantalum capacitor and a second metal plate of the silicon nitride capacitor. Further, a set of metal contacts is provided to each end of the tantalum strip to provide the tantalum resistor.

Lumped passive components and method of manufacture

A phase shifter includes three cascade interconnected phase shift stages. Each stage includes a quadrature coupler and a pair of field effect transistors (FET), having a pair of gates, a drain, and a source, connected in a common (grounded) source configuration. The drain of each FET is coupled to an input port of the quadrature coupler to provide two signal paths having an electrical pathlength difference corresponding to a 90.degree. differential phase shift. In the third stage, a length of transmission line is coupled between a drain of one of the FET's and one input port of the coupler to provide a signal path having an electrical pathlength corresponding to a 180.degree. phase shift. An input signal is fed to one of the gates of each FET of the first stage, and voltage level control signals are fed to the second one of gates of each FET of the first stage, to control the amplitude of the signal coupled to each drain. The phase shift of the input signal at the output of the quadrature coupler is selected by controlling the ratio of the amplitudes of the signals coupled to each drain. The phase shift of the input signal through succeeding stages is selected in response to a second set of control signals fed to the second gates of each FET which select the signal paths through each stage.

Variable phase shifter

A field effect transistor is provided wherein a semiconductor body has a central source region and a plurality of drain regions disposed about the periphery of the central source region. A gate region, common to at least a portion of the plurality of drain regions, is also formed in the body. With such arrangement an efficient multi-drain field effect transistor is provided through the use of a central source electrode formed on the semiconductor body.

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Newton, MA, United States of America

James L Vorhaus