Honeywell International Inc.

University of South Florida

Other

James L Tucker

Scott G Fleischman

William John Dalzell, Jr

Romney R Katti

Kenneth Henry Heffner

Anuj Kohli

Thomas Cordella

John D Profumo

Robert Compton

Jeffrey James Kriz

Eric E Vogt

Kara L Warrensford

Gregor D Dougal

Roy L Turknett

Takatoshi Yano

Paul S Fechner

James B Hobbs

Brian R Bernier

Gary Roosevelt

Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.

Wafer trust via location locked circuit layout with measurable integrity

In some examples, a programmable device may load configuration data into a configuration storage to configure programmable logic of the programmable device. The programmable device may include a key generation logic that may read at least a portion of the configuration data from the configuration storage. The key generation logic may generate a cryptographic key based at least in part on the at least a portion of the configuration data read from the configuration storage.

Configuration based cryptographic key generation

A circuit package for electrically connecting a plurality of modules. The circuit package having a first and second mounting plate, each including a plurality of module connectors configured to receive and form electrical connections with the plurality of modules. The circuit package also having a first and second sidewall mounted to the first and second mounting plates. The first sidewall including a plurality of sidewall fins extending outward from the first sidewall so that the plurality of sidewall fins are positioned between the first and second mounting plates and at least partially interleave with the plurality of modules.

Circuit packages including modules that include at least one integrated circuit

A system may encrypt the contents of a memory using an encryption key that is generated based on an entropy-based key derivation function. The system may generate a random value as a key split associated with an instance of writing data to memory. The system may generate an encryption key for encrypting the data using an entropy-based key derivation function based at least in part on the key split. The system may encrypt the data using the encryption key. The system may store the encrypted data and the key split to the memory.

Encryption using entropy-based key derivation

The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.

Integrated circuit stack including a patterned array of electrically conductive pillars

In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an integrated circuit die, which may not include any through-silicon vias that provide a pathway to an adjacent integrated circuit layer, and an interposer portion, which includes electrically conductive through-vias. The interposer portion may facilitate communication of the integrated circuit die with other integrated circuit layers of the integrated circuit system. In some examples, the stacked integrated circuit system may include more than one integrated circuit die, which may be in the same integrated circuit layer as at least one other integrated circuit die, or may be in a different integrated circuit layer.

Integrated circuit stack

A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.

Stacking arrangement for integration of multiple integrated circuits

Spread spectrum clocking circuitry may be configured to produce a spread spectrum clock signal that coordinates the actions of functional circuitry. Spread spectrum clocking circuitry may be configured to include delay circuitry configured to generate a random delay signal based on a random input value and generate the spread spectrum clock signal based on the random delay signal. By introducing true randomness into the delay signal, spread spectrum clocking signal may be able to generate a truly random, as opposed to a merely pseudo random, clock signal.

Spread spectrum clock generation using a tapped delay line and entropy injection

In some examples, a controller is configured to generate a key based on a physics-based output of a component. The controller may, for example, use the key to authenticate communication between at least two nodes, to encrypt data, or to decrypt data. In some examples, the component includes one or more subcomponents, each subcomponent including a cell filled with a gas, a light source configured to transmit a light through the gas cell, and a photodetector configured to sense light transmitted through the gas cell. The photodetector of each subcomponent is configured to generate an electrical signal that changes as a function of one or more properties of the light sourced by the light source, transmitted through the gas cell. The output of the component can is based on the signals generate by the one or more photodetectors.

Physics-based authentication

Systems and methods for a wafer scale atomic clock are provided. In at least one embodiment, a wafer scale device comprises a first substrate; a cell layer joined to the first substrate, the cell layer comprising a plurality of hermetically isolated cells, wherein separate measurements are produced for each cell in the plurality of hermetically isolated cells; and a second substrate joined to the cell layer, wherein the first substrate and the second substrate comprise electronics to control the separate measurements, wherein the separate measurements are combined into a single measurement.

Systems and methods for a wafer scale atomic clock

This disclosure describes techniques that may prevent cryptographic devices, including both encryption devices and decryption devices, from producing a power signature that can be used by attackers to deconstruct a cryptographic algorithm and extract a cryptographic key. The techniques may include an external power supply charging an internal, dedicated power storage element; temporarily gating off the encryption device from the external power supply; configuring a cryptographic logic unit to perform a cryptographic algorithm from power stored in the power storage element while the external power source is gated off; and then recharging the power storage element upon the cryptographic logic unit completing an iteration of the cryptographic algorithm.

Cryptographic logic circuit with resistance to differential power analysis

A device having a first oscillator circuit configured to generate a first signal with a first frequency based on an analog input and external characteristics, and a second oscillator circuit configured to generate a second signal with a second frequency based on a constant voltage and the external characteristics. The device also having one or more discrete logic gates configured to generate a digital composite signal based on the first signal and the second signal, such that a number of transitions in the digital composite signal over a period of time, based on the first frequency of the first signal, are indicative of the analog input.

Growing community of inventors

Clearwater, FL, United States of America

James L Tucker