Xilinx, Inc.

James L Saunders

Sudip K Nag

Jason Helge Anderson

Srinivasan Dasasathyan

Guenter Stenz

Rajeev Jayaraman

Krishnan Anandh

Madabhushi V R Chari

Jason H Anderson

Rajat Aggarwal

Qiang Wang

Guenther Stenz

Pavanish Nirula

Guenter Stentz

Method and apparatus are described for a placer system for placing design objects onto an arrayed architecture, such as a programmable logic device including an FPGA. More particularly, a placer interface is described for communicating with a placer core. The placer interface receives information from external entities, and unifies and generalizes this information for the placer core. The external entities comprise different representations of architecture, design, device, constraints and algorithm-dictated placer-movable objects.

Unified placer infrastructure

A method () of designing a programmable logic device can include the steps of identifying a cost function that penalizes floorplans of a circuit design that do not fit on the programmable logic device () and defining modules having components of a same type (). A set of shapes associated with a module can be determined (). The circuit design can be annealed () to determine a floorplan using the cost function and the set of shapes for the module.

Method system and apparatus for floorplanning programmable logic designs

A method () of placing local clock nets in a circuit design can include identifying the local clock nets for the circuit design and selecting components corresponding to each local clock net (), and assigning initial locations to each component of the local clock nets (). The method further can include generating at least one cost function () to evaluate () different placements of components of the local clock nets. The components () of the local clock nets () can be annealed () using one or more of the cost functions to assign locations to each component of the local clock nets.

Automated local clock placement for FPGA designs

Method and apparatus for recognizing data path structures in a netlist. The stages in the netlist are identified. Each stage includes a set of components that process multiple bits. The buses that connect the stages are also identified. A graph is generated to represent the stages and buses. The vertices in the graph represent the stages and the edges represent the buses. The graph is divided into subgraphs having terminating vertices that represent memory elements. Each subgraph represents a data path structure.

Recognizing structure information from a netlist

A method and apparatus for placement into a programmable gate array of I/O design objects having different I/O attributes. The I/O attributes of an I/O design object define the electrical characteristics of the design object. The programmable gate array has a plurality of sites (IOBs) arranged into banks supporting a variety of electrical interface characteristics. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between I/O attributes of I/O design objects as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, sets of I/O attributes are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.

Method and apparatus for placement of input-output design objects into a programmable gate array

A method and apparatus for placement into a programmable gate array of input-output (I/O) design objects having different voltage standards. The programmable gate array has a plurality of sites arranged into banks supporting interfaces with a plurality of different input and output voltage standards. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between design object voltage standards as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, standards are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.

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Mountain View, CA, United States of America

James L Saunders