Motorola Corporation

James L Rutledge

Kenneth Kaskoun

James Jen-Ho Wang

J B Price

Edwin E Reed

A test substrate (30) including a plurality of solder bumps (38) is used to test a die (10) which can be used as either a wire-bonded device or a flip-chip device. Die (10) includes test pads (14) which are redundant electrical connections to bond pads (12). The solder bumps make contact with the test pads of the device during testing. On separating the test substrate and die, the bumps remain on the test substrate if the die is to be wire bonded, or are transferred to the die if the die is to be flip-chip mounted to a next-level package substrate. Whether the bumps are transferred or not is determined by the relative areas of the solder receiving pads/studs (26 and 36) on the test substrate die. Common process flows and even die layouts can be used for the two different device types, thereby saving manufacturing and design costs.

Method for testing a semiconductor device and semiconductor device

A first pattern of bumps and a second pattern of bumps are formed on a substrate (10) with bumps (14,15). During a transfer process, only the bumps (14) of the first pattern of bumps are transferred to pad extensions (20) of a device (17). The bumps (15) of the second pattern of bumps are not affected by this process and can be later transferred to a second device.

Substrate for transferring bumps and method of use

Apparatus for the nitridiation of a silicon-bearing substrate is disclosed. The apparatus includes a double walled reaction vessel having first and second concentric walls bounding a reaction volume. Temperature of the reaction volume is controlled by resistance heaters located outside the outermost of the two concentric tubes. Plasma electrodes are positioned about the reaction volume and between the two concentric tubes. The ambient between the two tubes is controlled to protect the electrodes from oxidation at the high temperatures to which they are exposed. An rf generator is coupled to the plasma electrodes and is controllable independently from the resistance heaters.

Plasma enhanced thermal treatment apparatus

A static MOS RAM cell is provided that is resistant to inadvertent change of state due to charged particles striking the cell without decreasing write time. First and second cross-coupled transistors are coupled between first and second nodes, respectively, and a first voltage. First and second loads are coupled between the first and second nodes, respectively, and a second voltage. A first coupling transistor is coupled between the first node and a first input terminal, and has a gate coupled for receiving a write signal. A second coupling transistor is coupled between the second node and a second input terminal, and has a gate coupled for receiving the write signal. First and second variable loads are coupled between the first node and a gate of the second latching transistor, and the second node and a gate of the first latching transistor, respectively, for providing a resistance in the standby mode and relatively no resistance in the write mode.

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Austin, TX, United States of America

James L Rutledge