Texas Instruments Corporation

James L Gula

Peter D Vogt

Daniel E Schneider

An interrupt system provides interrupt signals to devices to be interrupted by indicating the presence of interrupts in a random access memory associated with each of the devices to be interrupted. The address of the interrupt signal that is written is assigned to a respective one of a plurality of addresses, each of which is assigned to a respective one of a plurality of interrupting devices and is indicative of the priority of the interrupt. The controller associated with each of the devices to be interrupted causes a scan of the associated memory and when an interrupt is detected, the address of the interrupt is sent to the interrupted device. The interrupted device then recognizes the interrupt by reason of its address and performs the appropriate interrupt routine. When an interrupt is written into the memory, a comparison is made of the address of the newly written interrupt with the address of the last scanned position. If the last scanned position has an address of higher priority than that of the newly written interrupt, scanning begins at the last scanned position. Otherwise, the newly written interrupt is read and its address sent to the interrupted device. Scanning commences from that point. The address of the last scanned positioned is compared with the address sent to the interrupted device to determine whether there has been a reference made to the memory in the time between the scanning of the last scanned position and the newly written interrupt. If the address of a last scanned position is of a lower priority, than the address sent to the interrupted device, scanning proceeds from a predetermined address.

Dynamic redirection of interrupts

A digital computing system includes at least a first and a second bus with at least a first master connected to the first bus and a second master connected to the second bus. The first master is capable of requesting the second bus through the first bus and the second master is capable of requesting the first bus through the second bus. Central conversion means receives both requests and has circuitry for generating a response signal to the first bus when both requests come simultaneously. The first master receives the response signal and continues the cycle, but without continuing the request for the second bus. The cycle is completed as though the request had been completed.

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James L Gula