Thinking Machines Corporation

Mitsubishi Electric Research Laboratories, Inc.

James L Frankel

Steven J Sistare

Karen C Jourdenais

Joseph W Marks

David B Anderson

Joshua E Simons

Linda J Seamonson

Steven N Goldhaber

Michael L Best

Edmund M Sullivan

A method for decorating a virtual world model first builds a physical model from a plurality of building blocks. Each building block includes a microcontroller coupled to a plurality of connectors. The connectros are for physically and electronically connecting the blocks in a three-dimensional structure to form the model. An arrangement of the blocks in the model is derived by connecting the model to a host computer. The arrangement is expressed as a set of logical axioms. The set of logical axioms is processed by a logic program to identify large scale structural elements of the model, and decorative attributes are assigned to the large. scale structural elements.

Method for decorating a virtual model

In a self-configuring store-and-forward computer network, a plurality of processors are each housed in an enclosure having a top surface and a bottom surface. Each processor has an associated block identification number. An array of m by n radially symmetric connectors are arranged on the top surface and on the bottom surface of each enclosure. Each connector has an associated connector identification number. The connectors physically and electronically couple the plurality of processors as a three-dimensional structure. Communications controller in each of the processors exchange the block and connector identification numbers between the processors and a host computer to determine an ordered list of connector numbers that is used to route messages between any of the processors and the host computer.

Self-configuring store-and-forward computer network

Provided is a method for routing messages among arbitrarily connected processors. Each processor is housed in an enclosure including a top surface and a bottom surface, and an array of m by n radially symmetric connectors are arranged on the top surface and on the bottom surface of the enclosure to interconnect the processors as a rigid three-dimensional structure. An unique block identification number is associated with each processor. A unique connector identification number is associated with each connector of a particular processor. A message is generated to include an ordered list of connector identification numbers, and the message is forwarded to a destination process according to the ordered list.

Message-routing protocol for arbitrarily connected processors frankel

A compiler for compiling a computer program wherein the computer program is adapted for use with a data parallel computer. The compiler comprises a front end which generates a parse tree from a source code. In generating the parse tree, the front end coordinates the compilation of type conversion operations and promotion operations such that run-time efficiency is maximized. In other words, the front end compiles the type conversion operations and promotion operations in an order which maximizes run-time efficiency.

System and method for multilevel promotion

An optimizer for optimizing an intermediate representation (IR) tree having multiple nodes. The IR tree represents a partial compilation of a source code. The source code is written using a high level language supporting data parallel processing. According to the present invention, the optimizer optimizes the IR tree by minimizing the number and size of temporary parallel variables in the IR tree. Such minimization optimizes the IR tree because temporary parallel variables require an enormous amount of space in memory.

System and method for parallel variable optimization

A compiler for compiling a computer program which is adapted for use with a data parallel computer. The compiler supports variables which involve parallelism. Variables which involve parallelism are parallel variables, templates for parallel variables called shapes, and pointers to parallel variables. For each variable involving parallelism declared globally in the source code, the compiler of the present invention emits in the target code a declaration of a global scalar variable. It further emits in the target code a start trap. When executed, the start trap allocates memory and a data structure for the global variables involving parallelism. The start trap also initializes the data structures and global variables involving parallelism. Finally, the compiler of the present invention emits in the target code one or more statements which, at run time, will cause the start trap to be invoked before the execution of any statement in which one of the global variables involving parallelism is read from or written to.

System and method for compiling a source code supporting data parallel

A compiler for compiling a computer program wherein the computer program is adapted for use with a data parallel computer. The compiler comprises an optimizer which optimizes the compiled code. In optimizing the compiled code, the optimizer performs live variable analysis. With regard to performing live variable analysis, the optimizer of the present invention is adapted for use with data parallel languages. Additionally, the optimizer is computationally efficient at compile time. Further, the optimizer operates in an incremental manner.

Compiler for performing incremental live variable analysis for

The present invention is directed towards a compiler for processing parallel communication instructions on a data parallel computer. The compiler of the present invention comprises a front end, a middle end, an optimizer, and a back end. The front end constructs a parse tree which includes nodes representative of parallel communication instructions. The middle end generates an intermediate representation (IR) tree from the parse tree. The IR tree includes general parallel communication IR nodes representative of target code to carry out parallel communication with general communication. An efficient parallel communication module of the optimizer replaces general parallel communication IR nodes with grid parallel communication IR nodes where doing so would result in more efficient target code. The grid parallel communication IR nodes represent target code to carry out parallel communication instructions with grid communication. The back end generates target code from the optimized IR tree.

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Lexington, MA, United States of America

James L Frankel