Unisys Corporation

James L Federici

Mitchell A Bauman

Kelvin S Vartti

Donald C Englin

Donald W Mackenthun

Gary J Lucas

Robert Marion Malek

Lewis A Boone

A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from managing the process of flushing old data from the second level cache memory. In the present invention, the second level cache memory is a store-in memory. Therefore, when data is to be deleted from the second level cache memory, a determination is made whether the data has been modified by the processor. If the data has been modified, the data must be rewritten to lower level memory. To free the second level cache memory for storage of the newly requested data, the data to be flush is loaded into a flush buffer for storage during the rewriting process.

Method for managing flushes with the cache

A method of and apparatus for improving the efficiency of a data processing system employing multiple dayclocks using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from dedicating a separate individual dayclock to each of the multiple instruction processors within the data processing system thereby decreasing access time and user queuing. These individual dayclocks are each incremented at one microsecond intervals. However, these individual dayclocks require periodic synchronization to avoid system level time-tagging problems. This synchronization occurs at 20 microsecond intervals using the cache coherency maintenance hardware of the system.

Use of a cache ownership mechanism to synchronize multiple dayclocks

A method of interfacing multiple requests using a request hold register, a multiplexer and a snapshot register with multiple requests directed into both the request hold register and a multiplexer which prevents forwarding the requests to the snapshot register if the snapshot register is not in a receiving condition but if the snapshot register is in a receiving condition allows the request to immediately enter snapshot register without having to wait for the next clock cycle.

Interface queue with bypassing capability for main storage unit

A serial speed-matching buffer for transferring data signals between a selectable one of multiple transferring units to one or more receiving units. The serial speed-matching buffer has a plurality of registers which may each be selectably configured in load mode to receive data signals from selectable ones of the transferring units. Data signals provided to the speed-matching buffer from a selectable one of the transferring units may be made available to the receiving unit during the next clock period. This is an improvement over a rank-of-registers speed-matching buffer which generally inflicts a delay prior to the first word of any transfer. When not conditioned in load mode, each of the registers defaults to a serial chain mode in which data signals may be received from an associated adjacent one of the registers, and wherein a predetermined one of the registers provides data signals at the receiving rate. Any register not containing valid buffered data signals is available to receive data signals from a transferring unit, thereby resulting in a design which requires fewer registers. Because the registers default to a serial chain mode when not receiving data from a selectable one of the transferring units, control logic for the buffer is simplified.

Serial speed-matching buffer utilizing plurality of registers where each

Method and apparatus for detecting and correcting memory storage data errors in a system utilizing parity error detection. An error detected in the memory storage device results in a parity error being reported, thereby causing the corresponding address location to be deactivated. Once deactivated, no further reading or writing is performed at that address location for a predetermined time period. The parity error reporting and address deactivation is accomplished without an access time penalty and requires a reduced number of I/O pins.

Second level cache having instruction cache parity error control

An apparatus for and method of efficiently providing a modular dayclock within a data processing system. This is accomplished by dividing the dayclock hardware into a number of dayclock modules configured to operate in a bit serial fashion. This allows the dayclock to accommodate a variety of dayclock word widths by simply varying the number of dayclock modules provided. Further, since the dayclock may operate serially, rather than in parallel fashion, the number of dayclock module I/O's and board route channels may be substantially reduced. Finally, all control logic may be provided directly in the dayclock modules, thereby eliminating the need for a central dayclock controller.

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Shoreview, MN, United States of America

James L Federici