National Semiconductor Corporation

James L Dunkley

Robert C Dobkin

James E Solomon

Thomas M Frederiksen

Victor K Liang

A semiconductor device wherein surface stabilization is provided by a shallow layer of ion implanted doping material on the surface of the semiconductor and beneath the passivating oxide layer. One embodiment is a bipolar transistor including a collector region, a base region and an emitter region, the base region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a zener diode device with an anode region and a cathode region, the cathode region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a JFET with a gate region and a source and drain region and a channel region extending through the gate region between the source and drain regions, the channel region being provided with the shallow ion implanted layer at the surface thereof.

Semiconductor device with an ion implanted stabilization layer

Process for manufacturing a JFET with an ion implanted stabilization

A zener diode in which the anode region of a first conductivity material is formed by diffusion in a semiconductor body, a cathode region of a second conductivity material is formed by diffusion in the semiconductor body, and the two regions are bridged by a third region extending through the two regions, the third region being a shallow layer of ion implanted doping material of said first conductivity type. In one embodiment, the anode and cathode regions are spaced-apart; in a second embodiment the cathode region is formed within the anode region. The ion implanted layer has a concentration that peaks below the surface, thus establishing the breakdown point for the avalanching of the zener diode below the surface and removed from surface contaminants such as found in the oxide surface layer.

Zener diode incorporating an ion implanted layer establishing the

A collector diffused isolation transistor wherein the normal buried layer in the substrate of the device is utilized as a collector region, an isolation region of the same conductivity type as the buried layer being formed by ion implantation of suitable atoms in the buried layer region with a second similar ion implantation in the surface of the epitaxial layer of second conductivity type grown over the substrate and buried layer, the collector diffused isolation region being formed by the up diffusion of the lower ion implanted region into the grown layer and the down diffusion of the upper ion implanted region into the grown layer so that the up and down diffusions overlap. Complimentary devices such as PNP and NPN devices are made on the same substrate utilizing this novel technique.

Complementary bipolar transistors having collector diffused isolation

Current scaling in a lateral transistor wherein a plurality of emitter-collector circuits are established, certain of said circuits having a different base width than certain other of said circuits. In one embodiment, separate transistors are formed, each with its own emitter and collector, each portion of each collector being spaced an equal distance from its associated emitter the base widths of the different transistors being different, such that, with the emitters coupled in common, different currents being dependent on the base width of the associated transistor. In a second embodiment, a common emitter is employed with the separate collectors formed as arcs about the emitter, the base widths between the emitter and the different collectors being different.

Growing community of inventors

Santa Clara, CA, United States of America

James L Dunkley