Xilinx, Inc.

James L Burnham

Gary R Lawman

Joseph D Linoff

Steven Hennick Kelem

Alan M Frost

Eric J Crabill

Smitha Sundaresan

James L McManus

A method is provided for watermarking FPGA configuration data. Specifically, if an end user desires to use a macro from a macro vendor, the end user creates a design file containing a marked macro received from the macro vendor, rather than the actual macro. The end user then uses an FPGA programming tool to convert the design file into configuration data. Specifically, the FPGA programming tool processes the design file to detect marked macros. If a marked macro is detected, the FPGA programming tool embeds a watermark corresponding to the macro within the configuration data.

Method of watermarking configuration data in an FPGA by embedding the watermark corresponding to a macro obtained upon encountering a first watermark tag from the macro

Methods and systems are provided in which logic cores from different third party core providers can be integrated for use with a single logic core generator. Core information from the various core providers is collected and formatted into a format that can be utilized by the single logic core generator. The information that is collected comprises at least one, and typically a number of different files. In some embodiments, the relevant core information is captured through the use of a graphical user interface (GUI) that guides particular core providers through a series of dialogs that capture the information. A formatting computer then takes the information and formats it into a form that can be utilized by the particular logic core generator. In the described embodiment, the information is formatted into at least one XCD file, which can then be utilized by the logic core generator. The newly-formatted cores can then be distributed to particular users for use with the core generator.

Methods and systems for providing logic cores from third party logic core providers

A core for a register-based programmable logic device includes a register configured to provide a hidden identifier in response to a secret unlock operation. The identifier is inaccessible during normal operation of the core implementation. The unlock operation is selected to be an action or set of actions that would typically not be performed during normal use of the core implementation. The logic associated with providing the hidden identifier in response to the unlock operation is configured to not interfere with normal operation of the core implementation. Therefore, the presence of this source identification capability is transparent to regular users (and unauthorized copyists) of the core implementation. The availability of the secondary identifier can be limited in duration to minimize the chances of accidental, or even intentional, discovery.

Method for watermarking a register-based programmable logic device core

A field programmable gate array (FPGA) is provided that can selectively accept or reject selected software (macros). Specifically, configuration data for the FPGA is passed through a configuration port to a decoder. The decoder processes the configuration data to detect locked macros. If a locked macro is detected, the decoder attempts to unlock the locked macro using one or more keys stored in a key table of the FGPA. If an appropriate key is in the key table, the decoder unlocks the locked macro to configure the FPGA. The keys can be pre-programmed into the FGPA by the macro vendor. If configuration data containing a locked macro is used with an FPGA without the appropriate key, configuration of the FPGA fails.

FPGA customizable to accept selected macros

A method is provided for configuring an FPGA to accept or reject selected software (macros). Specifically, if an end user desires to use a locked macro from a first macro vendor a locked macro from a second macro vendor in the same FPGA, a key manager prepares a keyed FPGA for the end user by pre-programming an FPGA with a first key, which is configured to unlock the first locked macro, and a second key, which is configured to unlock the second locked macro. The key manager obtains the first key from the first macro vendor and the second key from the second macro vendor. The keys are stored in a key table of the FPGA that is write-only from outside the FPGA. The end user pays a fee to the key manager for the keyed macro, but is not given access to the keys. The key manager apportions the fee from the end user and distributes appropriate licensing fees to the first macro vendor and the second macro vendor.

Methods to securely configure an FPGA to accept selected macros

A method is provided for securely configuring an FPGA with macros. Specifically, if an end user desires to use a macro from a macro vendor, the end user creates a design file containing an encrypted macro received from the macro vendor rather than the actual macro. The end user uses a FPGA programming tool to convert the design file into configuration data. Specifically, the FPGA programming tool processes the design file to detect encrypted macros. If an encrypted macro is detected, the FPGA programming tool requests authorization over a secured medium to decrypt the encrypted macro from the macro vendor. If authorization is received, the FPGA programming tool decrypts the encrypted macro and converts the design file into configuration data incorporating the macro.

Methods to securely configure an FPGA using encrypted macros

A method is provided for securely configuring an FPGA with macros. Specifically, if an end user desires to use a macro from a macro vendor, the end user creates a marked design file containing a macro marker rather than the actual macro. The marked design file is converted into configuration data by a macro manager. Specifically, the macro manager obtains the macro from the macro vendor and replaces the macro marker with the macro prior to converting the design file into configuration data. The macro manager provides the configuration data to the end user. Because only the macro manager has access to the macro, the possibility of unlicensed use of the macro is diminished.

Methods to securely configure an FPGA using macro markers

A method and circuit is provided for creating multiple product lines from a single silicon implementation of an integrated circuit (IC). Specifically, logic blocks within the IC are selectively disabled after manufacturing the IC to create various ICs of different functionality from a single silicon implementation of the IC. In one embodiment, a first logic block of the IC is coupled to a disable circuit by a first disable line and a second logic block of the IC is coupled to the disable circuit by a second disable line. The disable circuit can disable the first logic block by driving the first disable line to a disable logic state. Similarly, the disable circuit can disable the second logic block by driving the second disable circuit to the disable logic state. In an FPGA embodiment of the present invention, the first logic block is a row of configurable logic blocks (CLBs) and the second logic block is a column of CLBs.

Integrated circuit with selectively disabled logic blocks

A decryption scheme is provided for encrypted configuration bitstreams in a programmable logic device. One embodiment includes circuitry for altering a decryption key for a plurality of encrypted bitstream portions, thereby providing a high level of security of the circuit layout embodied in the bitstream.

Growing community of inventors

Morgan Hill, CA, United States of America

James L Burnham