Motorola Corporation

James L Broseghini

J Greg Viot

James M Sibigtroth

John A Langan

Eytan Hartung

John P Dunn

Thomas J Poterek

Michael I Catherwood

James G Viot

Donald H Lenhert

Greg Viot

A data processor (12) has built-in circuitry for scan testing certain circuits. The data processor generates and stores test vectors in a memory system (22) normally used for data and instruction storage. These vectors can be much larger than the size of any scan chain. During testing, the stored vectors are automatically routed to the circuits to be tested (36, 38) and the outputs compared to a benchmark. The data processor (12) need not pause to generate additional test vectors. Therefore, the data processor (12) can use a single circuit to generate scan data and compress scan results with minimal timing or size implications.

Method and apparatus for scan testing with extended test vector storage

A method and apparatus for unstacking registers in a data processing system (100). In one form, the present invention is a more time efficient solution to the problem of unstacking and stacking registers (154-158) during interrupt processing in a data processing system (100). By taking advantage of the fact that pulling a register value off of the stack does not change any of the values stored in the memory which is being used as the stack, the present invention reduces the unstacking and stacking each time that two interrupts are processed back to back with no non-interrupt processing in between. The present invention eliminates the unstacking of the program counter register (158) and the restacking of registers (154-158) by changing the value of the stack pointer register (161) without any corresponding stacking or unstacking operation.

Method and apparatus for unstacking registers in a data processing system

A method and apparatus for generating pseudo-random numbers or for performing data compression in a data processor (12). In one form, the present invention generates pseudo-random numbers which are used to provide scan input data bits during built-in-self-test (BIST) scan testing. The present invention then performs data compression on the scan output data received back from the circuits under test (73-75). In one embodiment, the BIST scan testing of data processor (12) is performed in a special 'background self-test mode'. Central processing unit (CPU) 20 is used to generate the pseudo-random numbers and to perform the data compression. CPU 20 also functions as a standard CPU when in a normal operating mode.

Method and apparatus for generating pseudorandom numbers or for

A data processing system (10) performs indexed addressing, autoincrementing, and autodecrementing using power of two byte boundaries. For example, a 5-bit offset allows a user to progress sixteen bytes either forward or backward through a table of data. An instruction specifying an operation to be performed, a pointer register (58, 60), and an offset value is provided to an execution unit (14). The pointer register (58, 60) stores a first address value and the offset value has a sign and a magnitude. An arithmetic logic unit, ALU, (52) inverts the sign of the offset value to provide an inverted sign value. A plurality of adders (100, 102, 104, 106, and 108) adds the offset value, the first address value, and the inverted sign value to generate an offset sum. A positive offset value is increased by one to generate a symmetric power of two offset range.

Data processing system for generating symmetrical range of addresses of

A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single 'MEM' software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. An operand assignment circuit (50) and an ALU (56) allow circuit (14) to determine the degree of membership more quickly. Assignment circuit (50) determines a multiplier for a multiplication operation based on a number of significant bits in the values to be multiplied. If the multiplier is smaller than the multiplicand, shorter multiplication operations may be performed. Additionally, ALU (56) operates in a split mode of operation which is able to perform two eight bit subtraction or multiplication operations concurrently which also results in these operations being performed more efficiently.

Circuit and method for determining membership in a set during a fuzzy

A circuit (14) to evaluate a plurality of fuzzy logic rules in a data processor (10) in response to a single 'REV' software instruction. The REV instruction evaluates the rules stored in a memory (32) to determine a rule strength of each. Antecedents are separated from consequences of each of the rules by a buffer address. To evaluate the antecedents, an ALU (52) subtracts an antecedent in memory (32) from a current antecedent stored in an accumulator (58). Subsequently, a swap logic (46) provides control information to assign a minimum value as a rule strength of the rule. Similarly, a maximum rule strength is required during evaluation of the consequences. ALU (52) subtracts a consequence in memory (32) from a consequence stored in accumulator (58). Depending on a result, swap logic (46) provides control information to assign a maximum rule strength to the consequences of the evaluated rule.

Circuit and method for evaluating fuzzy logic rules

A digital data processor is capable of performing limited modulo arithmetic. The base, M, of the modulo arithmetic to be preformed by the processor must be equal to 2.sup.X, where X is an integer. The method and apparatus is particularly useful for generating addresses for a circular buffer or queue data structure and avoids both the large amount of hardware required for general modulo arithmetic and the software overhead associated with the use of linear arithmetic to generate modulo addresses. According to this method, X is represented as a first digital value. This representation of X is ANDed with a second digital data value (an offset). The result is then ADDed linearly with a third digital data value (a current address with the buffer). During this addition process, certain carry-out signals are inhibited from propagating, according to the digital representation of X.

Method and apparatus for performing restricted modulo arithmetic

An adder circuit that has an encoded carry input, where a bit position weight of the carry input is two, allows the adder circuit to selectively concurrently add a data value of two to a first and a second input data operand of the adder circuit. The adder circuit is also able to add the first and second input data operands with a second carry input that is not encoded. A recoded multiplier combines two partial product calculations into one calculation during only a first partial product calculation operation by using the adder circuit. Partial product calculations are reduced in number during a multiply operation of a data processor.

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Austin, TX, United States of America

James L Broseghini