Intersil Corporation

Silicon Power Corporation

Other

Harris Corporation

Excelitas Technologies Corp.

James Kevin Azotea

Kenneth Brandmier

John E Waldron

Victor A Temple

Homer Glascock

Steve Arthur

A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be ON to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn ON. After the at least one IGBT turns ON, the at least one GTO is configured to turn OFF. After a predetermined amount of time, reflecting the post fabrication alteration to the GTO's minority carrier lifetime (e.g. electron irradiation), after the at least one GTO turns OFF, the at least one IGBT is configured to turn OFF. Alternatively, the circuit is used as an inverter switch, where at the command to turn ON is supplied, the at least one IGBT is turned ON, followed by the at least one SGTO. When commanded to turn OFF the at least one SGTO is turned OFF followed by the at least one IGBT. This alternative configuration allows the robust, controllable switching speeds of IGBTs and the superior conduction efficiency of SGTOs. The two configurations mentioned above utilize a wide range of SGTO performance, thus the ability to control the SGTOs turn-off speed by reducing its minority carrier lifetime after the device is processed is of large importance. The efficiency of all uses of the circuit can be optimized with the judicious selection of SGTO minority carrier lifetime and the ratio of active area between the SGTO and IGBT devices. In all cases there is a balance between the time the circuit can achieve hard turn-off without current commutation, the conduction efficiency of the circuit and the maximum amount of controllable current. In all cases both the conduction efficiency of the circuit is higher than an IGBT-only based circuit, and the switching performance is higher than a GTO-only based circuit.

Low-loss and fast acting solid-state breaker

A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be on to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn on. After the at least one IGBT turns on, the at least one GTO is configured to turn off. After a predetermined amount of time after the at least one GTO turns off, the at least one IGBT is configured to turn off.

A novel apparatus for cooling, supporting, and packaging power electronics. An elongated heat exchanger having a rectangular cross-section may carry and cool plural electronic devices. Plural heat exchangers may be arranged to form a chassis for two-sided cooling. Electronic devices on the heat exchangers may be interconnected and configured using circuitry bonded to a power pack cover. Circuitry on the cover, e.g., for reducing internal inductance, CTE mismatch and preventing voltage overshoot at turn-off, may be cooled through physical connections with electronic devices carried by the heat exchangers.

Heat exchanging chassis

A novel and apparatus for cooling, supporting, and packaging power electronics. An elongated heat exchanger having a rectangular cross-section may carry and cool plural electronic devices. Plural heat exchangers may be arranged to form a chassis for two-sided cooling. Electronic devices on the heat exchangers may be interconnected and configured using circuitry bonded to a power pack cover. Circuitry on the cover, e.g., for reducing internal inductance, CTE mismatch and preventing voltage overshoot at turn-off, may be cooled through physical connections with electronic devices carried by the heat exchangers.

Heat exchanging chassis and method

A hermetic thin pack semiconductor device. The semiconductor device has a semiconductor substrate and at least one electrode on the upper surface of the semiconductor substrate. A lid of a ceramic material for the semiconductor device has at least one opening extending through the lid. A first electrically conductive material is located on the interior surface of the at least one opening, a second electrically conductive material is located on at least a portion of the upper surface of the lid, and a third electrically conductive material is located on at least a portion of the lower surface of the lid. A solder material is positioned between the electrode and the third electrically conductive material and positioned on a corresponding portion of the electrode opposite a corresponding opening in the lid.

Hermetic thin pack semiconductor device

A power pack for providing power electronics at high temperature with high dI/dt, current, and voltage capability. The power pack having three layers. A top layer for providing: a matching composite Coefficient of Thermal Expansion (CTE) between power device materials and power electrodes, thermal cooling, and electrical conduction paths. The top layer may have interface circuitry for driving and controlling on-board power semiconductor devices. The top layer may also include traces and pads for the attachment of a gate, a gate return, and terminals. A middle layer may be a power semiconductor device providing control of the current flow. The bottom layer may be a rigid base plate for providing structural rigidity or may provide an electric and thermal path for the power semiconductor device. The power pack also includes a thermal shim which provides a thermal path to dissipate heat generated by the interface circuitry. The power pack may also include a snubber circuit.

Semiconductor power pack

A circuit and method for interrupting an AC load current includes a first MOS Controlled Thyristor (MCT) for selectively interrupting the load current. The current through the first MCT is reduced when the load current is to be interrupted by providing a pulse resonant commutation (PRC) current through the first MCT which flows in a direction opposed to the AC load current direction and which has a magnitude reducing the current through the first MCT to an MCT 'off' condition (e.g., when a voltage across the MCT is reversed, when there is near zero current through the MCT, or when a current is within the MCT's SOA.) The first MCT turns itself off when MCT gate voltage is an 'on' voltage and when reverse voltage is across the MCT. An MCT 'off' voltage may then be provided by sensing MCT current and providing an 'off' voltage to the MCT gate when the sensed current indicates that the MCT is an 'off' condition. The PRC current is generated by a second MCT which is triggered with a brief gate pulse when the load current is to be interrupted. The load current also may be sensed and the gate pulse triggered in the second MCT to interrupt the load current when the load current exceeds a predetermined value.

Growing community of inventors

Saratoga Springs, NY, United States of America

James Kevin Azotea