Freescale Semiconductor,inc.

International Business Machines Corporation

Globalfoundries Inc.

Motorola Corporation

James Kenyon Schaeffer, Iii

Srikanth Balaji Samavedam

Olubunmi O Adetutu

Dina H Triyoso

Unoh Kwon

William James Taylor, Jr

David Gilmer

Cristiano Capasso

Takashi Ando

Vijay Narayanan

Bich-Yen Nguyen

Gauri V Karve

Philip J Tobin

Murshed Mahmud Chowdhury

Eric D Luckowski

Mark Victor Raymond

Darrell Roan

Keith Kwong Hon Wong

Richard Stephan Wise

Ravikumar Ramachandran

Renee Tong Mo

Siddarth A Krishnan

Michael P Belyansky

Naim Moumen

Hongwen Yan

Kimberly Gay Reid

Daniel J Jaeger

Todd Christopher Bailey

Rama I Hegde

Byoung W Min

Hsing H Tseng

Marc A Rossow

Vidya S Kaushik

David C Sing

Melissa O Zavala

Daniel Thanh-Khac Pham

Sherry G Straub

James P Geren

Ying H Tsang

Srinivas V Pietambaram

Amy L Child

Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and a conductive material (e.g., an oxygen-gettering conductive material) overlying the high-k dielectric layer. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.

Transistors and semiconductor devices with oxygen-diffusion barrier layers

A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.

Scavenging metal stack for a high-K gate dielectric

A method and apparatus are described for fabricating metal gate electrodes () over a high-k gate dielectric layer () having a rare earth oxide capping layer () in at least the NMOS device area by treating the surface of a rare earth oxide capping layer () with an oxygen-free plasma process () to improve photoresist adhesion, forming a patterned photoresist layer () directly on the rare earth oxide capping layer (), and then applying a wet etch process () to remove the exposed portion of the rare earth oxide capping layer () from the PMOS device area.

Method of enhancing photoresist adhesion to rare earth oxides

A method and apparatus are described for fabricating single metal gate electrodes () over a high-k gate dielectric layer () that is separately doped in the PMOS and NMOS device areas () by forming first capping oxide layer () with a first dopant species on a high-k gate dielectric layer () in at least the NMOS device area and also forming second capping oxide layer () with a second dopant species on a high-k gate dielectric layer () in at least the PMOS device area, where the first and second dopant species are diffused into the gate dielectric layer () to form a first fixed charge layer () in the PMOS device area of the high-k gate dielectric area and a second fixed charge layer () in the NMOS device area of the high-k gate dielectric area.

CMOS integration with metal gate and doped high-K oxides

Methods are provided for fabricating a transistor. An exemplary method involves depositing an oxide layer overlying a layer of semiconductor material, forming an oxygen-diffusion barrier layer overlying the oxide layer, forming a layer of high-k dielectric material overlying the oxygen-diffusion barrier layer, forming a layer of conductive material overlying the layer of high-k dielectric material, selectively removing portions of the layer of conductive material, the layer of high-k dielectric material, the oxygen-diffusion barrier layer, and the oxide layer to form a gate stack, and forming source and drain regions about the gate stack. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.

Semiconductor device with oxygen-diffusion barrier layer and method for fabricating same

A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.

Process for making a semiconductor device using partial etching

Embodiments of the present invention provide a method of forming gate stacks for field-effect-transistors. The method includes forming a metal-containing layer directly on a first titanium-nitride (TiN) layer, the first TiN layer covering areas of a semiconductor substrate designated for first and second types of field-effect-transistors; forming a capping layer of a second TiN layer on top of the metal-containing layer; patterning the second TiN layer and the metal-containing layer to cover only a first portion of the first TiN layer, the first portion of the first TiN layer covering an area designated for the first type of field-effect-transistors; etching away a second portion of the first TiN layer exposed by the patterning while protecting the first portion of the first TiN layer, from the etching, through covering with at least a portion of thickness of the patterned metal-containing layer; and forming a third TiN layer covering an areas of the semiconductor substrate designated for the second type of field-effect-transistors.

Method of forming gate stack and structure thereof

A semiconductor device structure is formed over a semiconductor substrate and has a gate dielectric over the semiconductor substrate and a gate over the gate dielectric. The gate, at an interface with the gate dielectric, comprises a transition metal, carbon, and an electropositive element. The transition metal comprises one of group consisting of tantalum, titanium, hafnium, zirconium, molybdenum, and tungsten. The electropositive element comprises one of a group consisting of a Group IIA element, a Group IIIB element, and lanthanide series element.

Semiconductor device having a metal carbide gate with an electropositive element and a method of making the same

A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.

Method for forming a dual metal gate structure

A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.

Method of making metal gate transistors

A resistive device () and a transistor () are formed. Each uses a portion of a metal layer () that is formed at the same time and thus additional process steps are avoided to remove the metal from the resistive device. The metal used in the resistive device is selectively treated to increase the resistance in the resistive device. A polycrystalline semiconductor material layer () overlies the metal layer in the resistive device. The combination of these layers provides the resistive device. In one form the metal is treated after formation of the polycrystalline semiconductor material layer. In one form the metal treatment involves an implant of a species, such as oxygen, to increase the resistivity of the metal. Various transistor structures are formed using the untreated portion of the metal layer as a control electrode.

Semiconductor device with integrated resistive element and method of making

A method includes forming a first gate dielectric layer over a semiconductor layer having a first and a second well region, forming a first metal gate electrode layer over the first gate dielectric, forming a sidewall protection layer over the first metal gate electrode layer and adjacent sidewalls of the first gate dielectric layer and first metal gate electrode layer, forming a channel region layer over the second well region, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and second metal gate electrode layer over the channel region layer and over the second well region.

A stack located over a substrate. The stack includes a layer between a dielectric layer and a metal layer. The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example the control electrode stack is a gate stack for a MOSFET. In one example, the layer includes aluminum fluoride.

Method of forming a semiconductor device having an interlayer and structure therefor

A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer () over a gate dielectric layer (), forming a transition layer () over the first conductive layer using an atomic layer deposition process in which an amorphizing material is increasingly added as the transition layer is formed, forming a capping conductive layer () over the transition layer, and then selectively etching the capping conductive layer, transition layer, and first conductive layer, resulting in the formation of an etched gate stack (). By forming the transition layer () with an atomic layer deposition process in which the amorphizing material (such as silicon, carbon, or nitrogen) is increasingly added, the transition layer () is constructed having a lower region (e.g.,) with a polycrystalline structure and an upper region (e.g.,) with an amorphous structure that blocks silicon diffusion.

ALD gate electrode

Growing community of inventors

Austin, TX, United States of America

James Kenyon Schaeffer, Iii