Cisco Technology, Inc.

Advanced Micro Devices Corporation

Spansion LLC.

James K Pan

Ning Cheng

Christy Mein Chu Woo

Kung-Shiuh Huang

Hsiu-Ling Lee

Shuchuan Yao

Razmik Mampourian

Tekai Liu

Kim-Hui Ng

Systems and methods are provided to facilitate the display of status information associated with a network device using a plurality of multi-function status indicators, such as light emitting diodes (LEDs). In one implementation, a network device includes a plurality of user-viewable status indicators adapted to display status information associated with the network device. The network device further includes a processor adapted to detect a plurality of event conditions at the network device. A logic circuit of the network device is adapted to determine first and second sets status information to be displayed by the status indicators. A control circuit of the network device is adapted to provide the status indicators with display states associated with the first and second sets of status information without requiring user interaction with the network device. The event conditions may be multiplexed to identify associations between the event conditions and the display states.

Network device providing multi-function status indicators

The present invention is a dual-level flash memory cell design that stores 3 or more bits of information per transistor. The dual-level memory cell stores two lower bits in a first level and stores an upper bit in a second level. The lower bits are programmed, erased and read by alternate modes of operation wherein active regions operate as source and drain, and then drain and source. The upper bit is programmed and erased independent of the lower bits. However, reading of the upper bit depends upon read values of the lower bits. Additional levels are employed to store more than 3 bits of information.

Dual-level stacked flash memory cell with a MOSFET storage transistor

The present invention relates to methods of fabricating dual-level flash memory cells. A first active region and a second active region are formed in a substrate. A trench is formed in the substrate between the first active region and the second active region. A first insulator dielectric is formed on the substrate and within the trench forming a vertical structure. A first poly layer is formed on the first insulator dielectric. A second insulator dielectric is formed on at least a portion of the first poly layer. A second poly layer is formed on the second insulator dielectric.

Method of fabricating a dual-level stacked flash memory cell with a MOSFET storage transistor

Growing community of inventors

San Jose, CA, United States of America

James K Pan