Raytheon Company

James K Mathewes, Jr

H Frank Howes

Jack J Stiffler

Jan S Herman

Richard B Goud

Jan S Hermam

Stephen C Johnson

C W Eifrig

Charles O Schulz

Craig A Chancellor

Fault insertion circuits under programmable control and resident in an integrated circuit (LSI or VLSI) insert transient and intermittent fault classes in addition to a permanent fault class into functional logic on such integrated circuit. Specific fault types programmable for each fault class include a stuck-open fault and bridging faults both wired-AND and wired-OR. The programmable fault insertion circuitry on each integrated circuit interfaces directly or indirectly with a BIT maintenance controller. In addition to verifying test software, a fault tolerant system's error detection and recovery circuits may be verified by fault insertion testing using the transient and intermittent fault insertions.

Transient and intermittent fault insertion

A microprogrammed control unit of an information processing system having a control sequencer with dual microprogram counters for performing microdiagnostics simultaneously with performing macroprograms. The microdiagnostics comprise background and operability tests, the background tests being interleaved with macroinstruction operations under the control of the two independent microprogam counters. The background tests are run during processor idle time and the operability tests are executed at processor turn-on. The organization of the microdiagnostics into a hierarchical structure allows the use of the same microprogrammed test module for both the background and operability microdiagnostic tests. A prediction/residual coding technique provides fault detection for address and data information within the control sequencer.

Control sequencer with dual microprogram counters for microdiagnostics

Apparatus and method for providing programmable fault insertion circuitry in a large scale integrated (LSI) circuit device thereby eliminating the need for external switches or relays to create faults. A fault parameter word is stored in a register and the outputs of the register are decoded to select the fault condition to be inserted by an interfacing circuit to the logic being tested. Test vectors and the fault parameter word are generated by a controller coupled to the integrated circuit and a test response from the integrated circuit is examined by the controller.

LSI fault insertion

Growing community of inventors

Northborough, MA, United States of America

James K Mathewes, Jr