Sandisk Technologies Inc.

Sandisk Corporation

Advanced Micro Devices Corporation

Sandisk 3D LLC

Silicon Genesis Corporation

James K Kai

George Matamis

Johann Alsmeier

Vinod Robert Purayath

Takashi Whitney Orimoto

Henry Chien

Yuan Zhang

Murshed Chowdhury

Yanli Zhang

Masaaki Higashitani

Donovan Lee

Tuan Duc Pham

Raghuveer S Makala

Hiroyuki Ogawa

Tong Zhang

Fei Wang

Yao-Sheng Lee

Jixin Yu

Jin Liu

Henry Chin

George Samachisa

Senaka Kanakamedala

Koichi Matsuno

Jayavel Pachamuthu

Ching-Huang Lu

Yuki Mizutani

Yingda Dong

Wei Zhao

Lynne A Okada

Satoshi Shimizu

Michael A Bryan

Yasuo Kasagi

Rahul Sharangpani

Hiroyuki Kinoshita

Fumiaki Toyama

Zhixin Cui

Hisakazu Otoi

Sayako Nagamine

Akira Matsudaira

Yohei Masamori

Yoko Furihata

Kazuyo Matsumoto

Bhanwar Singh

Deepanshu Dutta

Xiang Yang

Christopher John Petti

Dana Lee

Mohan Dunga

Franz Kreupl

Masanori Tsutsumi

Akio Nishida

Venkatesh Ramachandra

Zhengyi Zhang

Zhenyu Lu

Kensuke Yamaguchi

Takaaki Iwai

Teruo Okina

Atsushi Suyama

Marika Gunji-Yoneoka

Piyush Dak

Luisa Lin

Jarrett Jun Liang

Makoto Koto

Takashi Orimoto

Joel Samuel Utz

Pamela G Dye

Erich W Denninger

Eric Thomas Sharp

Michael Ross Stamm

Robert Flores

Subhash Gupta

Roy E Scheuerlein

Ramkumar Subramanian

Jian Feng Chen

Nima Mokhlesi

Er-Xuan Ping

Angela Tai Hui

Peter Rabkin

Gerrit Jan Hemink

Man Lung Mui

Calvin T Gabriel

Fei Zhou

Lu You

William George En

Yung-Tin Chen

Wipul Jayasekara

Masatoshi Nishikawa

Xiying Costa

Steven J Radigan

Peng Zhang

Shinsuke Yada

Andrew C Lin

Kwang-Ho Kim

Abhijit Bandyopadhyay

Mitsuteru Mushiga

YenLung Li

Sateesh Koka

Yangyin Chen

Thomas Jongwan Kwon

Daxin Mao

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a plurality of source layers, where the electrically conductive layers include word lines and source-side select gate electrodes which are located between the plurality of source layers and the word lines in a vertical direction, groups of memory openings vertically extending through the alternating stack, and groups of memory opening fill structures located in the groups of memory openings. The plurality of source layers are laterally spaced apart and electrically isolated from each other, and each respective one of the plurality of source layers contacts at least one respective group of the groups of memory opening fill structures.

Three-dimensional memory device with separated source lines and method of making the same

A memory device includes a first memory block containing first word lines and a first source layer segment, and a second memory block containing second word lines and a second source layer segment which is electrically isolated from the first source layer segment. The first word lines in the first memory block are electrically connected to the respective second word lines in the second memory block.

Three-dimensional memory device including laterally separated source lines and method of making the same

A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.

Bonded semiconductor die assembly containing through-stack via structures and methods for making the same

The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line.

Low power read method and a memory device capable thereof

Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the unselected cells. The unselected cells share bit lines with the selected cells and may also share word lines. Preventing erase disturb may also include applying voltages to the select transistors that prevent the erase voltage from passing from the shared bit lines to the channels of the unselected cells. The voltages decrease from the bit lines to the unselected memory cells and may prevent GIDL generation. Current consumption is kept low.

Preventing erase disturb in NAND

A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

Three-dimensional memory device with separated contact regions and methods for forming the same

Technology is disclosed herein reconfiguring word lines as either data word lines or dummy word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines that provide electrical isolation between data word lines in a block. The block may be divided into an upper tier, a middle tier, and a lower tier, with the reconfigurable word lines within the middle tier. In a full-block mode the reconfigurable group of the word lines are used as data word lines. Because the reconfigurable word lines are used as data word lines in the full-block mode storage capacity is greater in the full-block mode than in the sub-block mode. Moreover, because the sub-blocks are smaller in size but greater in number than the full-blocks, the memory system may be provisioned with fewer blocks and still meet user storage requirements in both the full-block mode and the sub-block mode.

Dynamic word line reconfiguration for NAND structure

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and at least one drain-select-level isolation structure vertically extending through at least a topmost electrically conductive layer among the electrically conductive layers. The at least one drain-select-level isolation structure may include wiggles and cut through upper portions of at least some of the memory opening fill structures, or may include a vertically-extending dielectric material portion and laterally-protruding dielectric material portions adjoined to the vertically-extending dielectric material portion and laterally protruding into lateral recesses located adjacent to the at least the topmost electrically conductive layer.

Three-dimensional memory device with wiggled drain-select-level isolation structure and methods of manufacturing the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and an array of memory opening fill structures extending through the alternating stack, an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies, and a drain-select-level isolation strip including an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion.

Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same

A three-dimensional memory device includes an alternating stack of word lines and at least one insulating layers or air gaps located over a substrate, a memory opening fill structure extending through the alternating stack. The memory opening fill structure includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The word lines are thicker than the insulating layers or air gaps.

Three-dimensional memory device employing thinned insulating layers and methods for forming the same

An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.

Non-volatile memory with memory array between circuits

A memory element is provided that includes a portion of a bit line plug, a portion of a source line plug, a portion of a word line, a portion of a vertical semiconductor pillar disposed between the bit line plug, the source line plug and adjacent the word line, and a gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the word line.

Three dimensional ferroelectric memory

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A source power supply network can be formed on the backside of the source layer.

Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer

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San Francisco, CA, United States of America

James K Kai