Advanced Micro Devices Corporation

James Joseph Montanaro

Richard T Witek

Stephen Charles Kromer

Kathryn Jean Hoover

Daniel William Bailey

Bradley Gene Burgess

Aaron S Rogers

Peter J Hannan

Suzanne Plummer

Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.

Pipeline power gating

An integrated circuit () includes a firewall input terminal, a first circuit (), and a second circuit (). The firewall input terminal is for receiving a firewall input signal. The first circuit () is coupled to a first power supply voltage terminal () and has an output for providing a control signal. The second circuit is coupled to a second power supply voltage terminal (), to the firewall input terminal (), and to the first circuit (). When the firewall input signal is inactive, an activation of the control signal affects the operation of the second circuit. When the firewall input signal is active, an activation of the control signal does not affect the operation of the second circuit.

Integrated circuit with a hibernate mode and method therefor

A data processing system () comprises a system bus (), a plurality of devices () coupled to the system bus (), a bus monitor circuit (), and a clock generator (). The plurality of devices () includes at least one bus master () which is capable of performing accesses on the system bus (). The bus monitor circuit () is coupled to the at least one bus master (), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (). The clock generator () has an output coupled to at least one of the plurality of devices () and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.

Method and apparatus for lowering bus clock frequency in a complex integrated data processing system

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Austin, TX, United States of America

James Joseph Montanaro