Lucent Technologies Inc.

Digital Equipment Corporation

Compaq Computer Corporation, Inc.

James Jonathan Delmonico

Andrew Halstead Mason

Reinhard C Schumann

The present invention is an IC (inter-IC control) bridge device which implements a communication protocol layered on top of a standard IC protocol. The layered protocol used by the bridge device is termed the 'Layered IC Protocol'&#x2014;abbreviated 'LIP'. Thus the bridge device is called a &#x201c;LIP bridge device&#x201d;. The LIP bridge device provides IC address extension, data integrity checking, and fault detection and isolation when inserted between an IC bus master and it's intended target IC device. Each LIP bridge device has at least two attached IC busses&#x2014;a parent bus and a child bus. The LIP bridge operates as a slave on its parent bus, and a master of its child bus. The Layered IC protocol is specified to operate on a bus between one or more bus masters and the parent bus of one or more LIP bridge devices. The child bus is used for attaching multiple IC devices and/or one or more LIP bridge devices. In an exemplary implementation, the LIP bridge device is constructed using a microcontroller to create a LIP bridge device with one parent and one child IC bus port and a group of LIP bridge configuration pins. The parent bus traffic to a given LIP bridge device consists entirely of LIP packets, and the child bus traffic consists of standard IC packets to communicate with standard child bus IC devices. The child bus traffic may also consist of LIP packets to communicate with LIP bridges attached to the child bus. By design, the LIP packets and standard IC transactions do not interfere with one another. The LIP bridge device interprets LIP command packets from a bus master and translates them into the intended IC data stream that is then broadcast over the child bus. Likewise, data from the child bus is used to create LIP packets that are returned to the proper bus master. The use of LIP packets on a given IC bus provides an extra level of IC addressing.

Expansion bridge apparatus and method for an I2C bus

A method for reducing power consumption in a computer system is provided wherein the computer system includes a system bus interface connected by a signal line to a power supply and/or clock circuitry for the central processing unit, each having the capability to change the characteristic of its output responsive to the signal line for placing the central processing unit in a low-power consuming state. The system bus interface chip further including a storage location and counter for storing the type and quantity of interrupt assertions during the period of time when the central processing unit is in the low power consuming state. The system software determines the desired period of time to put the central processing unit into the low-power consuming safe and does not return it to normal power consuming state until the time period has expired, a non interval clock interrupt is asserted, or another critical event occurs that needs immediate CPU attention. When one of these conditions arises, the signal line changes polarity, the power supply and/or clock circuitry returns normal operating levels to the CPU, and the system bus interface presents all interrupts that asserted while the CPU was in the low-power consuming state to the CPU so it can continue normal operation.

Skipping clock interrupts during system inactivity to reduce power

A method for reducing power consumption in a computer system is provided wherein the computer system includes a system bus interface connected by a signal line to a power supply and/or clock circuitry for the central processing unit, each having the capability to change the characteristic of its output responsive to the signal line for placing the central processing unit in a low-power consuming state. The system bus interface chip further including a storage location and counter for storing the type and quantity of interrupt assertions during the period of time when the central processing unit is in the low power consuming state. The system software determines the desired period of time to put the central processing unit into the low-power consuming state and does not return it to normal power consuming state until the time period has expired, a non interval clock interrupt is asserted, or another critical event occurs that needs immediate CPU attention. When one of these conditions arises, the signal line changes polarity, the power supply and/or clock circuitry returns normal operating levels to the CPU, and the system bus interface presents all interrupts that asserted while the CPU was in the low-power consuming state to the CPU so it can continue normal operation.

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Clinton, MA, United States of America

James Jonathan Delmonico