Motorola Corporation

James John Caserta

Kelvin E McCollough

In accordance with the present invention, a frequency modulating phase-locked-loop (FMPLL) (,) architecture is implemented. The frequency of the FMPLL (,) is controlled using a current controlled oscillator (ICO) (,). The ICO (,) receives a current signal incorporating feedback to maintain a fixed gain. The ICO (,) associated with the FMPLL (,) establishes a predictable change in the output frequency for a given change in its input controlled current (ICTL). Relying upon this fixed gain, a frequency shift can be created by summing in an additional delta current (IMOD) to the input control current. By periodically varying the magnitude of the current IMOD, a frequency modulated clock is produced at the output of the ICO,. The magnitude of IMOD controls the amount of frequency shift of the frequency modulated clock. By providing an IMOD signal which is proportional to the generated system frequency, a frequency shift proportional to the average, or center, frequency is produced. Therefore, the percentage of frequency modulation is constant regardless of the magnitude of the system clock frequency. By calibrating the output reference of a voltage reference source 146, the desired modulation frequency percent can be further met.

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Austin, TX, United States of America

James John Caserta