Advanced Micro Devices Corporation

Broadcom Corporation

Oracle America, Inc.

Lucent Technologies Inc.

Sun Microsystems, Inc.

Alcatel Lucent

Avago Technologies General IP (singapore) Pte. Ltd.

James Jiahua Yu

Andrew C Yang

Bhanwar Singh

Aly E Orady

Sebastian Turullols

Mike Morrison

Moon-Yee Wang

Hong-Gee Fang

Wael William Diab

Angela Tai Hui

Robin W Cheung

Kouros Ghandehari

Tiao-Hua Kuo

Sesha Thalpasai Panguluri

Michael S Chung

Minh Quang Tran

Aloysius T Tam

John Rigby

Moon S Kok

May-Lin Lee

Jiunn-Yau Liou

Tiao-Huo Kuo

System, method and apparatus for one-pair power over Ethernet in an automotive application. In one embodiment, a power sourcing equipment transmits a forward path current to a powered device via a single conductor pair and receives a return path current from the powered device via a chassis of an automotive vehicle.

System, method and apparatus for one-pair power over ethernet in an automotive application

A power over one-pair Ethernet approach. A data transformer is coupled to a single conductor pair using one or more direct current (DC) blocking elements that preserve an alternating current path. The data transformer enables a network device to transmit and receive data with a link partner device via the single conductor pair. Power transmission over the single conductor pair is enabled through the coupling of a power over Ethernet module to the single conductor pair using a diode that can be paired with a zener diode.

Power over one-pair Ethernet approach

A technique for classifying traffic at a network node includes programming multiple on-chip memory arrays with identical search entries, receiving multiple packets, and distributing classification searches related to the packets among the multiple on-chip memory arrays. In an embodiment, the on-chip memory arrays are content-addressable memory (CAM) arrays. In another embodiment, the distributing of classification searches related to the packets is performed in an alternating fashion with respect to a fixed order.

Classifying traffic at a network node using multiple on-chip memory arrays

Embodiments of power sourcing equipment (PSE) utilizing AC disconnect are provided herein. In one embodiment, a PSE is provided that includes a DC supply configured to provide a DC voltage over a data communications medium, a controller configured to provide an AC disconnect signal over the data communications medium, and a parallel inductor-capacitor (LC) circuit coupled between the DC supply and the data communications medium. The parallel LC circuit is configured to isolate the DC supply from the AC disconnect signal. In another embodiment, a PSE is provided that includes a DC supply configured to provide a DC voltage at an output, an inductor coupled between the output of the DC supply and a data communications medium, and a capacitor coupled between the data communications medium and ground. The inductor and capacitor form a series LC circuit configured to generate an AC disconnect signal.

AC disconnect of power over ethernet devices

A system for sharing a network port of a network interface includes a plurality of processing units, a first network interface unit coupled to a first portion of the plurality of processing units, a second network interface unit coupled to a different portion of the plurality of processing units, and a link coupled between the first and second network interface units. The first and second network interface units each includes an independently controllable network port for connection to a network, and a virtual interface. The network port includes a shared MAC unit, a link interface, and control logic, which may selectably route packets between processing units of the first portion of the plurality of processing units and the network via the link and the network port of the second network interface unit. The virtual interface may include a plurality of independent programmable virtual MAC units.

System for sharing a network port of a network interface including a link for connection to another shared network interface

A system and method for measuring a cable resistance in a power over Ethernet (PoE) application. A short circuit module in a powered device is designed to produce a short circuit effect upon receipt of a cable resistance detection voltage. The cable resistance detection voltage can be designed to be greater than a voltage for detection or classification and less than a voltage for powering of the powered device. The measurement of the current at a time when a short circuit effect is produced at the powered device enables a calculation of the actual resistance of the cable on a given PoE port.

System and method for measuring a cable resistance in a power over Ethernet application

A system includes one or more processing units coupled to a network interface unit. The network interface unit may include a network port for connection to a network and a virtual interface that may be configured to distribute an available communication bandwidth of the network port between the one or more processing units. The network port may include a shared media access control (MAC) unit. The virtual interface may include a plurality of processing unit resources each associated with a respective one of the one or more processing units. Each of the processing unit resources may include an I/O interface unit coupled to a respective one of the one or more processing units via an I/O interconnect, and an independent programmable virtual MAC unit that is programmably configured by the respective one of the one or more processing units. The virtual interface may also include a receive datapath and a transmit datapath that are coupled between and shared by the plurality of processing unit resources and the network port.

Shared virtual network interface

A multiplexing system having an input unit, a storage unit and control unit. The input unit receives data units corresponding to multiple source data streams and extracts packets from the data units. The control unit computes data rate estimates for the source data streams based on timestamps in the source data streams. The storage unit stores a packet count and previous timestamp value for each source data stream. The control unit computes a preliminary data rate estimate for a source data stream based on samples of a local clock if timestamps are not received promptly. The control unit also computes scheduling rates based on the data rate estimates. The scheduling rates are used to control the rates of allocation of data from the source data streams into a multiplexed output stream. The control unit computes scheduling rates in a way that avoids oversubscription of the output channel.

Rapid datarate estimation for a data stream multiplexer

A system including a memory (storing a set of data records), a digital phase-locked loop (PLL) and digital circuitry. Each of the data records is allocated to one packet stream in a set of packet streams. The digital circuitry is configured to: invoke a read operation from the memory in response to a received stream indicator and received channel indicator corresponding to a current timestamp-bearing packet; generate an output timestamp for the current packet equal to an expected timestamp provided by the memory as part of the read operation; and generate error data based on argument data including a received input timestamp, a received slot delay value, a previous source frequency estimate and an expected timestamp provided as part of the read operation. The digital PLL is configured to compute an updated source frequency estimate based on information including the error data and the previous source frequency estimate.

Sharing a digital phase-locked loop across multiple packet streams

System and method for measuring a cable resistance in a Power over Ethernet application

A packet stream multiplexer may include one or more control loops (e.g., digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop may slowly drive an error between a received timestamp and an estimated timestamp to zero. A second control loop may more quickly drive a first derivative of the error to zero. The second control loop may include a set of digital filters ordered according to tracking speed. The output of the slowest filter is initially selected for updating the source clock frequency estimate. As time progresses, the faster filters are selected in succession. The estimated source clock frequency is used to restamp packets of the packet stream as they are sent out onto an output channel.

Digital phase locked loops for packet stream rate matching and restamping

A technique for classifying traffic at a network node involves programming a content addressable memory (CAM) array with multiple class-specific entries, where each of the class-specific entries has an associated traffic class, obtaining a protocol-independent key field from an incoming packet, and searching the programmed CAM array with the protocol-independent key field to identify an associated traffic class of the incoming packet. In another embodiment, each of the class-specific entries has an associated traffic distribution policy, which may be applied to an incoming packet.

Classifying and distributing traffic at a network node

An exemplary method of using developer as a solvent to spread photoresist faster and reduce photoresist consumption can include dispensing a developer solution onto an integrated circuit wafer, spinning the integrated circuit wafer to distribute the developer solution over the integrated circuit wafer, and dispensing a photoresist solution onto the integrated circuit covered with the developer solution.

System for and method of using developer as a solvent to spread photoresist faster and reduce photoresist consumption

A method of fabricating an integrated circuit can include providing a layer of silicon nitride over a semiconductor substrate where the layer of silicon nitride has a first thickness selected based on a desired size of extensions; providing a layer of photoresist material over the layer of silicon nitride; patterning the layer of photoresist to form photoresist features being separated at the top of the photoresist features by one minimum lithographic feature and etching a portion of the layer of silicon nitride to form a hole for an integrated circuit device feature. The photoresist features include extensions at the bottom of the photoresist features. The extensions define footings. These footings reduce the separation at the bottom of the photoresist features. As such, exposed portions of the layer of silicon nitride are less than one minimum lithographic feature in width.

Method of using controlled resist footing on silicon nitride substrate for smaller spacing of integrated circuit device features

An exemplary method of depositing photoresist material on an integrated circuit wafer is described. This method can include providing a cross-shaped resist dispenser including a plurality of resist dispense nozzles; dispensing photoresist material through the plurality of resist dispense nozzles to an integrated circuit wafer; and rotating at least one of the cross-shaped resist dispenser and the integrated circuit wafer.

Growing community of inventors

Milpitas, CA, United States of America

James Jiahua Yu