General Electric Company

Globalfoundries Inc.

International Business Machines Corporation

James Jay McMahon

Xunyuan Zhang

Peter Micah Sandvik

Shao Beng Law

Sean Xuan Lin

Errol Todd Ryan

Stephen Daley Arthur

Peter Almern Losee

Nicholas V Licausi

Kevin Sean Matocha

Ljubisa Dragoljub Stevanovic

Avinash Srikrishnan Kashyap

Zachary Matthew Stum

Ryan Scott Smith

Lars W Liebmann

Michael Rizzolo

Cornelius Brown Peethala

Alexander Viktorovich Bolotnikov

Sergei Ivanovich Dolinsky

David Alan Lilienfeld

Hari Prasad Amanapu

Prasad Bhosale

Stanislav Ivanovich Soloviev

Sabarni Palit

Nicholas V LiCausi

Peter Almren Losee

Semiconductor devices including skip via structures and methods of forming the skip via structure include interconnection between two interconnect levels that are separated by at least one other interconnect level, i.e., skip via to connect Mx and Mx+2 interconnect levels, wherein the intervening metallization level (MX+1) is electrically isolated from the skip via. Cap layers in the metallization levels are pre-patterned to provide openings therein generally corresponding to locations of the skip via structure prior to high aspect ratio etching to form the skip via structure.

Skip via for metal interconnects

The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.

Metal interconnects for super (skip) via integration

The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to SiC super-junction (SJ) power devices. A SiC-SJ device includes a plurality of SiC semiconductor layers of a first conductivity-type, wherein a first and a second SiC semiconductor layer of the plurality of SiC semiconductor layers comprise a termination region disposed adjacent to an active region with an interface formed therebetween, an act wherein the termination region of the first and the second SiC semiconductor layers comprises a plurality of implanted regions of a second conductivity-type, and wherein an effective doping profile of the termination region of the first SiC semiconductor layer is different from an effective doping profile of the termination region of the second SiC semiconductor layer.

Edge termination designs for silicon carbide super-junction power devices

The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

Via and skip via structures

The present disclosure generally relates to semiconductor structures and, more particularly, to dielectric repair for via and skip via structures and methods of manufacture. The method includes: etching a via structure in a dielectric layer; repairing sidewalls of the via structure with a repair agent; and extending the via structure with an additional etching into a lower dielectric layer to form a skip via structure exposing a metallization layer.

A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

Method and system for a semiconductor device with integrated transient voltage suppression

A solid state photomultiplier includes at least one microcell configured to generate an initial analog signal when exposed to optical photons. The solid state photomultiplier further includes a quench circuit electrically coupled with the at least one microcell. The quench circuit includes at least one quench resistor configured to exhibit a substantially constant temperature coefficient of resistance over a selected temperature range.

Solid state photomultiplier with wide temperature range of operation

The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; an upper wiring layer with one or more wiring structures, located above the first wiring layer; a blocking material which contacts at least one of the wiring structures of the upper wiring layer; a skip via with metallization, the skip via passes through the upper wiring layer and makes contact with the one or more wiring structures of the first wiring layer; and a conductive material in the skip via above the metallization and in a via interconnect above the blocking material.

Skip via structures

In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

Silicon-carbide MOSFET cell structure and method for forming same

In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well () (P type) and two parallel sources () (N type) formed within the well. A plurality of source rungs () (doped N) connect sources () at multiple locations. Regions between two rungs () comprise a body () (P type). These features are formed on an N-type epitaxial layer (), which is formed on an N-type substrate (). A contact () extends across and contacts a plurality of source rungs () and bodies (). Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

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Clifton Park, NY, United States of America

James Jay McMahon