Taiwan Semiconductor Manufacturing Comp. Ltd.

James Jann-Ming Wu

Wen-Chuan Chiang

Bao Ru Yang

The poor uniformity of Interlevel Dielectric Deposition (ILD) thickness for High Aspect Ratio (HAR) contact after Chemical Mechanical Planarization (CMP) will cause serious underlayer loss due to the longer over-etching time that is required to compensate for thickness differences within the wafer. Prior Art uses 1.5K Plasma Enhanced Tetra-Ethyl-Ortho-Silicate (PETEOS) to serve as a stop layer and thus reduce underlayer loss. The present invention teaches using a non-silicon oxide containing SiN/SiON or Si,N,/SiON as a stop layer. The present invention therefore is aimed at reducing underlayer loss and thereby improving the uniformity of the underlayer thickness upon completion of the hole etching process. Concurrently, the over-etch time can be reduced to less than 10% of the time required for Prior Art contact hole etching.

Growing community of inventors

Hsin-Chu, Taiwan

James Jann-Ming Wu