Western Digital Technologies, Inc.

Intel Corporation

James J Walsh

Rajesh Koul

Rodney Norman Mullendore

Andrew John Tomlin

Daniel Lee Helmick

Jaya L Jeyaseelan

Shay Benisty

Songnan Yang

Stephen Gold

Emily B Cooper

David Meyer

Vivek Shivhare

Gary N Matos

Ronald W Gallahan

A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.

Extensible storage system and method

A storage system caches logical-to-physical address table entries read in volatile memory. The logical-to-physical address table entries are stored in codewords. The storage system can vary a number or size of an entry in a codeword. Additionally or alternatively, each codeword can store both complete and partial logical-to-physical address table entries. In one example, a codeword having 62 bytes of data and two bytes of error correction code stores 15 complete logical-to-physical address table entries and one partial logical-to-physical address table entry, where the remainder of the partial entry is stored in another codeword. This configuration strikes a good balance between storage space efficiency and random-access write performance.

Storage system and method for storing logical-to-physical address table entries in a codeword in volatile memory

The present disclosure generally relates to limiting bandwidth in storage devices. One or more bandwidth quality of services levels may be selected and associated with commands according to service level agreements, which may prioritize some commands over others. A storage device fetches and executes one or more the commands. Each of the commands is associated with a bandwidth quality of service level. After executing the commands and transferring the data to a host device, the storage device may delay writing a completion entry corresponding to the executed commands to a completion queue based on the associated bandwidth quality of service level of the commands. The device may then delay revealing the completion entry by delaying updating a completion queue head pointer. The device may further delay sending an interrupt signal to the host device based on the associated bandwidth quality of service level of the commands.

Bandwidth limiting in solid state drives

Systems and methods for quality of service (QoS) using adaptive command fetching are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device processes the commands through various phases including fetching, processing, posting a completion message, and sending an interrupt to the host. NVMe also includes an NVMe virtualization environment, which uses a subsystem with multiple controllers to provide virtual or physical hosts direct I/O access. QoS may be used so that the NVMe processes in the virtualization environment receive sufficient resources. In particular, bandwidth assigned to a submission queue may be considered when processing of commands (such as fetching of commands). In the event that the bandwidth assigned to the submission queue is exceeded, the processing of the commands (such as the fetching of the commands) may be delayed.

System and method for QoS over NVMe virtualization platform using adaptive command fetching

Extensible storage system controller

Disclosed is a wireless charging device for charging electronic devices placed within proximity of the transmitter of the wireless charging device. The wireless charging device includes an inductive coupler, a reflected power detector, a power source and a power control system. The inductive coupler is configured to charge at least one electronic device present in the charging area. The inductive coupler takes power form the power source. The inductive coupler is also capable of communicating with electronic devices being charged to exchange a set of information. In addition to notebook PCs, this solution can be extended to desktop and tablet PCs, slates and office furniture as pervasive means of wireless charging multiple devices.

Apparatus, systems and methods for wireless charging for PC platforms and peripherals

Techniques are disclosed involving coils. For example, energy may be transferred between transmitting and receiving coils. The transmitting coil may be in a first device, while the receiving coil may be in a second device. In embodiments, the transmitting coil may be shaped in a way as to direct a magnetic field toward a receiving device. Similarly, the receiving device may be shaped in a way that is directed towards the device having the transmitting coil.

Coil techniques

Disclosed herein are several methods and systems for handling atomic write commands that reach scattered address ranges. One embodiment includes a method of performing an operation in a data storage device, the method comprising: receiving an atomic write command; obtaining a plurality of ranges of logical addresses affected by the atomic write command; for each of the plurality of affected ranges, assigning metadata information to track completion of a write operation performed at that range; performing the write operations in the ranges of logical addresses; updating the metadata information upon completion of the write operations in the ranges; and deferring an update to a translation map of the data storage device until the metadata information has been updated.

Method and system for atomically writing scattered information in a solid state storage device

A method, apparatus, and system for coordinated link power management. Some embodiments of a method include receiving an exit latency for each of a group of link states for a link, with a device being coupled to an interconnect via the first link. A latency tolerance value is determined and communicated, and a platform latency is received. The method further provides for determining a link budget for the device, the link budget indicating an amount of time available for an exit from a link state for the device; and selecting one of the link states based at least in part on the link budget.

Growing community of inventors

Santa Clara, CA, United States of America

James J Walsh