Motorola Corporation

James J Stipanuk

Mark S Birrittella

Robert Bruce Davies

Warren J Schultz

A high voltage bridge interface circuit is provided for AC and brushless DC motor control having a high voltage isolation circuit and drive circuits which simplify the high voltage interface and reduce the total system integration effort. The isolation circuit provides the high voltage unilateral isolation between the control circuit and the high voltage power supply conductors, while the drive circuits improve the noise immunity at the gate termimals of the power MOSFET bridge. The high voltage bridge interface circuit is partitioned by providing the high voltage interface within one IC thereby permitting the integration of the discrete components of the power MOSFET drive circuits and simplifying the overall system integration.

High voltage bridge interface

A circuit for selecting a row of memory cells of an array is disclosed that reduces selection time, eliminates the need for providing a regulated voltage for biasing an active load, and utilizes the capacitive charge on the lower word line in the selection of the row. The array includes a first voltage terminal, a second voltage terminal, a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, wherein the plurality of memory cells are arranged in a matrix of rows and columns. Each of the cells in a row are coupled between the first voltage terminal and a word line, and each of the cells in a column are coupled between a pair of the bit lines. A word line driver circuit is coupled between bases of active load transistors in each of the memory cells in a row and the word line of that row for selecting that row of memory cells.

Circuit for biasing row of memory cells

A circuit for writing bipolar memory cells is provided that reduces power dissipation by requiring only a small voltage change on the bit lines between read and write modes. The memory circuit includes a first voltage terminal, a second voltage terminal, a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, wherein the plurality of memory cells are arranged in a matrix of rows and columns. Each of the cells in a row are coupled between the first voltage terminal and a word line, and each of the cells in a column are coupled between a pair of the bit lines. A word line driver circuit is coupled between the first voltage terminal and one of the word lines of each of the rows for selectively applying voltage to the one of the word lines. A decoder circuit is coupled to the bit lines for enabling current through the bit lines. A current source is coupled between the second voltage terminal and each of the decoder circuits for sinking a read current through the bit lines of each column. A write current source is switchably coupled between the decoder circuits and the second voltage terminal for sinking a write current through the bit lines of each column.

Circuit for writing bipolar memory cells

A memory cell is provided having reduced read and write times, and a large current dynamic range between the standby mode and the read mode. A pair of cross-coupled NPN transistors operating in the inverse mode have their emitters coupled to a word line and their collectors coupled to receive a supply voltage by a first and second load, respectively. First and second NPN sense transistors each have a base coupled to the base of one of the cross-coupled transistors, an emitter coupled to a first and a second bit line, respectively, and a collector coupled to receive the supply voltage.

Bipolar RAM cell

A memory cell is provided having reduced read and write times, and a large current differential between the standby mode and the read mode. A pair of cross-coupled NPN transistors have their emitters coupled to a lower word line and their collectors coupled to an upper word line by a first and second load, respectively. First and second NPN sense transistors each have a base coupled to the base of one of the cross-coupled transistors, an emitter coupled to a first and a second bit line, respectively, and a collector coupled to receive a supply voltage.

An interface circuit for interconnecting an integrated injection logic (I.sup.2 L) portion of an integrated circuit to a linear portion of an integrated circuit. The circuit transfers both logic information and I.sup.2 L current level references from the I.sup.2 L circuitry to the linear circuitry at the relatively large voltage levels present in linear circuitry. One embodiment employs a cascode arrangement involving one transistor, two diodes and a resistor. Another embodiment utilizes the matching characteristics of a pair of transistors operating in the forward and reverse modes respectively to perform the function with only one transistor.

Growing community of inventors

Chandler, AZ, United States of America

James J Stipanuk