Freescale Semiconductor,inc.

James J Riches

John J Parkes, Jr

Mahibur Rahman

James G Mittel

Raul Salvi

A digital tuning system () for changing a cutoff frequency of an analog filter () includes digital synthesizers (and) for producing a two-tone calibration signal () applied to an input of the filter after a quality factor of the filter is increased. The filter includes at least one R/C circuit with two resistors (and) for changing the quality factor and arrays (and) of capacitors for changing the cutoff frequency. The amplitude of the magnitude responses (and) of the filter to each tone (and) is measured by a two discrete Fourier transform single-frequency bin power detection circuits (and) while the filter is sequenced through a plurality of capacitance settings. An optimal capacitance for the R/C circuit is selected by comparing, to a pre-selected value, a difference between the responses of the filter to each tone, for each capacitance setting.

Controlling the bandwidth of an analog filter

A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.

Clock jitter minimization in a continuous time sigma delta analog-to-digital converter

A resistor capacitor (RC) tracking loop includes a parasitic insensitive integrator () charged by a buffer () with offset compensation. The integrator () operates to provide an accurate ramped voltage proportional to a measured RC time constant. A single comparator () is used for sensing the voltage ramp rate by detecting two multiplexed reference voltages (VV). A timer within controller () is triggered by the Vcrossing at comparator (). The timer counts the number of precision reference clock periods (F) that occur between the Vand Vcrossings and adjusts an accumulator within controller () to a value (M). This value (M) is directly used to adjust a resistor and/or capacitor array used in a continuous time filter whose bandwidth and corner frequency can be precisely tuned.

Offset, delay and parasitically immune resister-capacitor (RC) tracking loop and method of using same

An adaptive analog-to-digital converter (ADC) system () includes an automatic gain control (AGC) controller () for receiving both in-band and out-of-band signals from a radio frequency (RF) receiver and producing an AGC control signal therefrom. A digital signal processor (DSP) () is then used for interpreting the AGC control signal and providing an adjustment signal to an ADC (). The ADC () uses the adjustment signal to dynamically control efficiency of the ADC systemby adjusting bit resolution, reference capacitance and bias based upon the RF signal received and desired protocol requirements presented to the AGC controller ().

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Lake Worth, FL, United States of America

James J Riches